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@@ -91,6 +91,6 @@ THe CHIPS Alliance is hosted by The Linux Foundation, a 501(c)6 non-profit.</des
 Rob Mains - General Manager The General Manager works with the Governing Board, our members, and our projects to ensure the CHIPS Alliance is a healthy, sustainable, and neutral home for open source technical collaborations.</description></item><item><title>Interconnect Workgroup</title><link>https://chipsalliance.org/workgroups/interconnect/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/workgroups/interconnect/</guid><description>The Interconnect workgroup researches open networking protocols to facilitate direct coherency messaging between components such as processor caches, memory controllers, and various accelerators in RISC-V cores. The interconnections provided by this group play a crucial role in SoCs, chiplets, and various hardware designs. We offer design guidelines for interconnects and manage open-source interconnect IP based on these guidelines. Interconnect WG supports the advancement of the open-source hardware ecosystem.</description></item><item><title>Join</title><link>https://chipsalliance.org/join/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/join/</guid><description>The CHIPS Alliance is an organization which works collaboratively to develop high quality, open source hardware designs relevant to silicon devices and FPGAs. By sharing openly resources and ideas, we hope to lower the cost of hardware development.
 As a collection of open source projects, anyone is welcome to participate in the technical development process. The Technical Steering Committee is governed by a technical charter.
 The CHIPS Alliance also welcomes corporate members.</description></item><item><title>Members</title><link>https://chipsalliance.org/about/members/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/about/members/</guid><description>When an organization joins the CHIPS Alliance, they are making a tangible commitment to the success and sustainability of open source projects which help to achieve these goals. The CHIPS Alliance recognizes the critical supporting role of these organizations, and thanks them for their ongoing support of our project communities.
-CHIPS Alliance Members Become a Member Platinum Members Gold Members Silver Members Auditor Members Associate Members</description></item><item><title>Projects</title><link>https://chipsalliance.org/projects/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/projects/</guid><description>Graduated Projects SV tests SystemVerilog test framework for checking SV spec support coverage in various open source tools - parsers, linters, formatters etc. Repositories: sv-tests Issue Tracker Website Contact: Tom Gorochowik (GitHub) F4PGA Free and open source toolchain for FPGA devices Repositories: f4pga Issue Tracker Website Contact: Tomasz Michalak (GitHub) FPGA tool perf Framework for automatic FPGA toolchains benchmarking Repositories: fpga-tool-perf actions Issue Tracker Website Contact: Tomasz Gorochowik (GitHub) RocketChip The SoC generator instantiates the RISC-V Rocket Core and relevant component.</description></item><item><title>Rocket Workgroup</title><link>https://chipsalliance.org/workgroups/rocket/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/workgroups/rocket/</guid><description>The Rocket Chip Workgroup covers the “Rocket” pipelined implementation of a RISC-V core as well as a TileLink uncore and cache coherent memory hierarchy. The main rocket-chip repository that the group maintains is a meta-repository containing tools needed to generate and test RTL implementations of SoC designs. This repository contains code that is used to generate RTL using Chisel and Diplomacy: the Rocket Chip generator itself is a Scala program that invokes the Diplomacy library and Chisel compiler in order to emit RTL describing a complete SoC.</description></item><item><title>Tools Workgroup</title><link>https://chipsalliance.org/workgroups/tools/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/workgroups/tools/</guid><description>The Tools workgroup (WG) of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design (as there is a separate Analog WG that focuses on AMS design flows). The topics covered include simulation, synthesis, place and route, IP aggregation, linting, formatting, and many more.</description></item><item><title>Who We Are</title><link>https://chipsalliance.org/about/who-we-are/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/about/who-we-are/</guid><description>The CHIPS Alliance leverages common hardware development efforts by developing IP blocks that can be broadly used, such as RISC-V cores and neural network accelerator cores. We recognize that verification contributions benefit all who participate in the project, and prioritize joint resources for design verification.
+CHIPS Alliance Members Become a Member Platinum Members Gold Members Silver Members Auditor Members Associate Members</description></item><item><title>Projects</title><link>https://chipsalliance.org/projects/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/projects/</guid><description>Graduated Projects Caliptra The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust Repositories: caliptra caliptra-rtl caliptra-sw caliptra-ureg caliptra-dpe Issue Tracker Website Contact: Andres Lagar-Cavilla (GitHub) F4PGA Free and open source toolchain for FPGA devices Repositories: f4pga Issue Tracker Website Contact: Tomasz Michalak (GitHub) FPGA Interchange format FPGA Interchange is a Vendor agnostic FPGA devices and designs description.</description></item><item><title>Rocket Workgroup</title><link>https://chipsalliance.org/workgroups/rocket/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/workgroups/rocket/</guid><description>The Rocket Chip Workgroup covers the “Rocket” pipelined implementation of a RISC-V core as well as a TileLink uncore and cache coherent memory hierarchy. The main rocket-chip repository that the group maintains is a meta-repository containing tools needed to generate and test RTL implementations of SoC designs. This repository contains code that is used to generate RTL using Chisel and Diplomacy: the Rocket Chip generator itself is a Scala program that invokes the Diplomacy library and Chisel compiler in order to emit RTL describing a complete SoC.</description></item><item><title>Tools Workgroup</title><link>https://chipsalliance.org/workgroups/tools/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/workgroups/tools/</guid><description>The Tools workgroup (WG) of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design (as there is a separate Analog WG that focuses on AMS design flows). The topics covered include simulation, synthesis, place and route, IP aggregation, linting, formatting, and many more.</description></item><item><title>Who We Are</title><link>https://chipsalliance.org/about/who-we-are/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/about/who-we-are/</guid><description>The CHIPS Alliance leverages common hardware development efforts by developing IP blocks that can be broadly used, such as RISC-V cores and neural network accelerator cores. We recognize that verification contributions benefit all who participate in the project, and prioritize joint resources for design verification.
 The scope of the Project includes hardware and software design and development under an open source (Apache v2) license:
 Verified IP blocks (compute cores, accelerators etc) Verified SoC designs (based on RISC-V and other open source cores) Open source software development tools for ASIC development High value IP including analog peripherals, mixed signal blocks and compute acceleration Exploration of new design flows such as Python-based design verification.</description></item></channel></rss>

news/analyze-verilator-processes/index.html

@@ -137,7 +137,7 @@ <h2 id=introducing-astsee>Introducing astsee</h2>
 <p><img src=Verilator-helper-tools--blog-CHIPS-Alliance-3.png alt="A view of the diff generation process in astsee"></p>
 <p>While being able to access raw JSON output from each verilation stage is useful, it still remains difficult to see patterns and points of failure when working with very large, complex and state-of the-art designs. This is particularly true when helping customers build production-grade chips that require incredible amounts of long-turnaround, compute-heavy workloads.</p>
 <p>To get more insight into the internals of Verilator in their work, Antmicro developed <a href=https://github.com/antmicro/astsee>the astsee suite</a>, which provides a comprehensive toolkit for pretty-printing, diffing, and exploring ASTs from a wide range of sources (including, but not limited to, Verilator). Astsee can generate an interactive HTML document from JSON output with a diff view, which provides a way to easily compare the original AST dump with the JSON representation. It is also possible to view two generated JSON dumps and compare them. One particularly useful feature of astsee is the ability to highlight a given part of the output in one pane when comparing AST to JSON, which will automatically highlight the same output on the other pane.</p>
-<p><img src=analyze-verilator-processes-and-asts--blog.gif alt="Interactive HTML diff view with JSON output"></p>
+<p><img src=analyze-verilator-processes-and-asts--blog4.png alt="Interactive HTML diff view with JSON output"></p>
 <p>Astsee also works as a plugin within <a href=https://www.sourceware.org/gdb/>GDB</a>, which allows users to invoke it for more granular dumps during the process of debugging in Verilator. Users can choose to execute astsee at any point during the verilation process, not only at the end of an individual stage, providing the possibility to identify and eradicate bugs that emerge during each stage of verilation. Currently, astsee only supports generic JSON trees, but support can be easily extended to other ASTs that have been exported into different formats as the suite operates functionally independently of other software.</p>
 <p>Support for Verilator is specifically provided through <a href=https://github.com/antmicro/astsee/blob/main/astsee/verilator_cli.py>astsee_verilator</a>, a tool which harnesses the power of astsee and Verilator using the JSON dumps obtained from the aforementioned &ndash;dump-tree-json tool. This tool also helps analyze individual nodes within the generated AST, as they can contain multiple different and important values such as pointers and data types. With this specific knowledge of how the node is composed, it is possible to compare fields separately. Astsee therefore provides tangible benefits in terms of reducing development time, as it provides the Verilator AST output in a clean and structured order which can then be modified as required without requiring difficult and time consuming comparisons.</p>
 <p><img src=Analyze-Verilator-processes-and-ASTs-with-the-astsee-suite--screenshot.png alt="Analyze Verilator process and ASTs with the ASTEE suite"></p>