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chipsalliance / chisel-template Public template

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Adding companion main class to generate GCD.v verilog source#126

Merged

jackkoenig merged 5 commits intochipsalliance:mainchipsalliance/chisel-template:mainfrom Martoni:generate_verilogCopy head branch name to clipboard

Mar 7, 2024

Conversation Commits5 (5)Checks Files changed

Commits

Commits on Mar 7, 2024

Adding companion main class to generate GCD.v verilog source
Martoni
committed
Remove verilog file if exists before generate it
Martoni
committed
Use emitSystemVerilogFile to simplify
Martoni
committed
Apply suggestions from code review
jackkoenig
authored
Merge branch 'main' into generate_verilog
jackkoenig
authored

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