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Fix Queue.apply for size 0 in chisel3._ code (#1177)
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3 files changed

+41
-2
lines changed

3 files changed

+41
-2
lines changed

src/main/scala/chisel3/util/Decoupled.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -277,7 +277,7 @@ object Queue
277277
pipe: Boolean = false,
278278
flow: Boolean = false): DecoupledIO[T] = {
279279
if (entries == 0) {
280-
val deq = Wire(new DecoupledIO(enq.bits))
280+
val deq = Wire(new DecoupledIO(chiselTypeOf(enq.bits)))
281281
deq.valid := enq.valid
282282
deq.bits := enq.bits
283283
enq.ready := deq.ready

src/test/scala/chiselTests/CompatibilitySpec.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks
9797
val dcd = Wire(Decoupled(data))
9898
dcd shouldBe a [DecoupledIO[UInt]]
9999
Queue(dcd) shouldBe a [DecoupledIO[UInt]]
100+
Queue(dcd, 0) shouldBe a [DecoupledIO[UInt]]
100101
Enum(UInt(), 2) shouldBe a [List[UInt]]
101102
ListLookup(wire, List(wire), Array((BitPat("b1"), List(wire)))) shouldBe a [List[UInt]]
102103
Lookup(wire, wire, Seq((BitPat("b1"), wire))) shouldBe a [UInt]

src/test/scala/chiselTests/QueueSpec.scala

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ class ThingsPassThroughTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int
2525
inCnt.inc()
2626
}
2727
when(q.io.deq.fire()) {
28-
//ensure that what comes otu is what comes in
28+
//ensure that what comes out is what comes in
2929
assert(elems(outCnt.value) === q.io.deq.bits)
3030
outCnt.inc()
3131
}
@@ -169,6 +169,33 @@ class QueueFlowTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: I
169169
}
170170
}
171171

172+
class QueueFactoryTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: Int) extends BasicTester {
173+
val enq = Wire(Decoupled(UInt(bitWidth.W)))
174+
val deq = Queue(enq, queueDepth)
175+
176+
val elems = VecInit(elements.map {
177+
_.asUInt()
178+
})
179+
val inCnt = Counter(elements.length + 1)
180+
val outCnt = Counter(elements.length + 1)
181+
182+
enq.valid := (inCnt.value < elements.length.U)
183+
deq.ready := LFSR(16)(tap)
184+
185+
enq.bits := elems(inCnt.value)
186+
when(enq.fire()) {
187+
inCnt.inc()
188+
}
189+
when(deq.fire()) {
190+
//ensure that what comes out is what comes in
191+
assert(elems(outCnt.value) === deq.bits)
192+
outCnt.inc()
193+
}
194+
when(outCnt.value === elements.length.U) {
195+
stop()
196+
}
197+
}
198+
172199
class QueueSpec extends ChiselPropSpec {
173200
// Disable shrinking on error.
174201
implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
@@ -233,4 +260,15 @@ class QueueSpec extends ChiselPropSpec {
233260
}
234261
}
235262
}
263+
264+
property("Queue companion object factory method should work") {
265+
forAll(vecSizes, safeUIntN(20), Gen.choose(0, 15)) { (depth, se, tap) =>
266+
whenever(se._1 >= 1 && se._2.nonEmpty) {
267+
assertTesterPasses {
268+
new QueueFactoryTester(se._2, depth, se._1, tap)
269+
}
270+
}
271+
}
272+
273+
}
236274
}

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