Merge branch '3.1.x' into release

Bump version

Author: ucbjrl

build.sbt

@@ -34,7 +34,7 @@ val defaultVersions = Map("firrtl" -> "1.1.7")
 
 lazy val commonSettings = Seq (
   organization := "edu.berkeley.cs",
-  version := "3.1.7",
+  version := "3.1.8",
   git.remoteRepo := "git@github.com:freechipsproject/chisel3.git",
   autoAPIMappings := true,
   scalaVersion := "2.11.12",

chiselFrontend/src/main/scala/chisel3/core/Bits.scala

@@ -55,6 +55,14 @@ private[chisel3] sealed trait ToBoolable extends Element {
   final def toBool(): Bool = macro SourceInfoWhiteboxTransform.noArg
 
   def do_toBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool
+
+  /** Casts this object to a [[Bool]]
+    *
+    * @note Width must be known and equal to 1
+    */
+  final def asBool(): Bool = macro SourceInfoWhiteboxTransform.noArg
+
+  def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool
 }
 
 /** A data type for values represented by a single bitvector. Provides basic
@@ -307,6 +315,13 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
     }
   }
 
+  final def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
+    width match {
+      case KnownWidth(1) => this(0)
+      case _ => throwException(s"can't covert UInt<$width> to Bool")
+    }
+  }
+
   /** Returns this wire concatenated with `other`, where this wire forms the
     * most significant part and `other` forms the least significant part.
     *

src/main/scala/chisel3/util/ImplicitConversions.scala

@@ -13,5 +13,5 @@ object ImplicitConversions {
   // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and
   // UInt.asUInt.
   implicit def intToUInt(x: Int): UInt = chisel3.core.fromIntToLiteral(x).asUInt
-  implicit def booleanToBool(x: Boolean): Bool = x.asBool
+  implicit def booleanToBool(x: Boolean): Bool = x.B
 }