Merge branch '3.5.x' into 3.5-release

Author: jackkoenig

core/src/main/scala/chisel3/Aggregate.scala

@@ -14,6 +14,7 @@ import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo._
 
+import java.lang.Math.{floor, log10, pow}
 import scala.collection.mutable
 
 class AliasedAggregateFieldException(message: String) extends ChiselException(message)
@@ -381,11 +382,30 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend
     compileOptions:      CompileOptions
   ): T = {
     require(!isEmpty, "Cannot apply reduction on a vec of size 0")
-    var curLayer: Seq[T] = this
-    while (curLayer.length > 1) {
-      curLayer = curLayer.grouped(2).map(x => if (x.length == 1) layerOp(x(0)) else redOp(x(0), x(1))).toSeq
+
+    def recReduce[T](s: Seq[T], op: (T, T) => T, lop: (T) => T): T = {
+
+      val n = s.length
+      n match {
+        case 1 => lop(s(0))
+        case 2 => op(s(0), s(1))
+        case _ =>
+          val m = pow(2, floor(log10(n - 1) / log10(2))).toInt // number of nodes in next level, will be a power of 2
+          val p = 2 * m - n // number of nodes promoted
+
+          val l = s.take(p).map(lop)
+          val r = s
+            .drop(p)
+            .grouped(2)
+            .map {
+              case Seq(a, b) => op(a, b)
+            }
+            .toVector
+          recReduce(l ++ r, op, lop)
+      }
     }
-    curLayer(0)
+
+    recReduce(this, redOp, layerOp)
   }
 
   /** Creates a Vec literal of this type with specified values. this must be a chisel type.

core/src/main/scala/chisel3/Bits.scala

@@ -1324,7 +1324,7 @@ sealed class Bool() extends UInt(1.W) with Reset {
   /** Logical or operator
     *
     * @param that a hardware $coll
-    * @return the lgocial or of this $coll and `that`
+    * @return the logical or of this $coll and `that`
     * @note this is equivalent to [[Bool!.|(that:chisel3\.Bool)* Bool.|)]]
     * @group Logical
     */
@@ -1336,7 +1336,7 @@ sealed class Bool() extends UInt(1.W) with Reset {
   /** Logical and operator
     *
     * @param that a hardware $coll
-    * @return the lgocial and of this $coll and `that`
+    * @return the logical and of this $coll and `that`
     * @note this is equivalent to [[Bool!.&(that:chisel3\.Bool)* Bool.&]]
     * @group Logical
     */

core/src/main/scala/chisel3/BlackBox.scala

@@ -157,7 +157,7 @@ abstract class BlackBox(
     _compatAutoWrapPorts() // pre-IO(...) compatibility hack
 
     // Restrict IO to just io, clock, and reset
-    if (!_io.forall(portsContains)) {
+    if (!_io.exists(portsContains)) {
       throwException(s"BlackBox '$this' must have a port named 'io' of type Record wrapped in IO(...)!")
     }
 

core/src/main/scala/chisel3/Clock.scala

@@ -23,7 +23,7 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element
 
   override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit =
     that match {
-      case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions)
+      case _: Clock | DontCare => super.connect(that)(sourceInfo, connectCompileOptions)
       case _ => super.badConnect(that)(sourceInfo)
     }
 

core/src/main/scala/chisel3/Data.scala

@@ -667,7 +667,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
     topBindingOpt match {
       // DataView
       case Some(ViewBinding(target)) => reify(target).ref
-      case Some(AggregateViewBinding(viewMap, _)) =>
+      case Some(AggregateViewBinding(viewMap)) =>
         viewMap.get(this) match {
           case None => materializeWire() // FIXME FIRRTL doesn't have Aggregate Init expressions
           // This should not be possible because Element does the lookup in .topBindingOpt

core/src/main/scala/chisel3/Element.scala

@@ -36,10 +36,15 @@ abstract class Element extends Data {
         case Some(litArg) => Some(ElementLitBinding(litArg))
         case _            => Some(DontCareBinding())
       }
-    case Some(b @ AggregateViewBinding(viewMap, _)) =>
+    // TODO Do we even need this? Looking up things in the AggregateViewBinding is fine
+    case Some(b @ AggregateViewBinding(viewMap)) =>
       viewMap.get(this) match {
-        case Some(elt) => Some(ViewBinding(elt))
-        case _         => throwException(s"Internal Error! $this missing from topBinding $b")
+        case Some(elt: Element) => Some(ViewBinding(elt))
+        // TODO We could generate a reduced AggregateViewBinding, but is there a point?
+        // Generating the new object would be somewhat slow, it's not clear if we should do this
+        //   matching anyway
+        case Some(data: Aggregate) => Some(b)
+        case _ => throwException(s"Internal Error! $this missing from topBinding $b")
       }
     case topBindingOpt => topBindingOpt
   }

core/src/main/scala/chisel3/Mem.scala

@@ -56,7 +56,9 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     with SourceInfoDoc {
   _parent.foreach(_.addId(this))
 
-  private val clockInst: Clock = Builder.forcedClock
+  // if the memory is created in a scope with an implicit clock (-> clockInst is defined), we will perform checks that
+  // ensure memory ports are created with the same clock unless explicitly specified to use a different clock
+  private val clockInst: Option[Clock] = Builder.currentClock
 
   protected def clockWarning(sourceInfo: Option[SourceInfo]): Unit = {
     // Turn into pretty String if possible, if not, Builder.deprecated will find one via stack trace
@@ -132,7 +134,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     implicit sourceInfo: SourceInfo,
     compileOptions:      CompileOptions
   ): T = {
-    if (warn && clock != clockInst) {
+    if (warn && clockInst.isDefined && clock != clockInst.get) {
       clockWarning(Some(sourceInfo))
     }
     makePort(sourceInfo, idx, dir, clock)
@@ -164,7 +166,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
   )(
     implicit compileOptions: CompileOptions
   ): Unit = {
-    if (warn && clock != clockInst) {
+    if (warn && clockInst.isDefined && clock != clockInst.get) {
       clockWarning(None)
     }
     implicit val sourceInfo = UnlocatableSourceInfo
@@ -223,7 +225,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     compileOptions:    CompileOptions
   ): Unit = {
     implicit val sourceInfo = UnlocatableSourceInfo
-    if (warn && clock != clockInst) {
+    if (warn && clockInst.isDefined && clock != clockInst.get) {
       clockWarning(None)
     }
     val accessor = makePort(sourceInfo, idx, MemPortDirection.WRITE, clock).asInstanceOf[Vec[Data]]

core/src/main/scala/chisel3/Printable.scala

@@ -18,7 +18,7 @@ import java.util.{MissingFormatArgumentException, UnknownFormatConversionExcepti
   * }}}
   * This is equivalent to writing:
   * {{{
-  *   printf(p"The value of wire = %d\n", wire)
+  *   printf("The value of wire = %d\n", wire)
   * }}}
   * All Chisel data types have a method `.toPrintable` that gives a default pretty print that can be
   * accessed via `p"..."`. This works even for aggregate types, for example:

core/src/main/scala/chisel3/VerificationStatement.scala

@@ -92,8 +92,8 @@ object assert {
   ): Assert = {
     val id = new Assert()
     when(!Module.reset.asBool()) {
-      Builder.pushCommand(Verification(id, Formal.Assert, sourceInfo, Module.clock.ref, cond.ref, ""))
       failureMessage("Assertion", line, cond, message, data)
+      Builder.pushCommand(Verification(id, Formal.Assert, sourceInfo, Module.clock.ref, cond.ref, ""))
     }
     id
   }
@@ -178,8 +178,8 @@ object assume {
   ): Assume = {
     val id = new Assume()
     when(!Module.reset.asBool()) {
-      Builder.pushCommand(Verification(id, Formal.Assume, sourceInfo, Module.clock.ref, cond.ref, ""))
       failureMessage("Assumption", line, cond, message, data)
+      Builder.pushCommand(Verification(id, Formal.Assume, sourceInfo, Module.clock.ref, cond.ref, ""))
     }
     id
   }

core/src/main/scala/chisel3/experimental/dataview/package.scala

@@ -97,11 +97,16 @@ package object dataview {
     val targetContains:  Data => Boolean = implicitly[DataProduct[T]].dataSet(target)
 
     // Resulting bindings for each Element of the View
-    val childBindings =
+    // Kept separate from Aggregates for totality checking
+    val elementBindings =
       new mutable.HashMap[Data, mutable.ListBuffer[Element]] ++
         viewFieldLookup.view.collect { case (elt: Element, _) => elt }
           .map(_ -> new mutable.ListBuffer[Element])
 
+    // Record any Aggregates that correspond 1:1 for reification
+    // Using Data instead of Aggregate to avoid unnecessary checks
+    val aggregateMappings = mutable.ArrayBuffer.empty[(Data, Data)]
+
     def viewFieldName(d: Data): String =
       viewFieldLookup.get(d).map(_ + " ").getOrElse("") + d.toString
 
@@ -130,7 +135,7 @@ package object dataview {
           s"View field $fieldName has width ${vwidth} that is incompatible with target value $tex's width ${twidth}"
         )
       }
-      childBindings(vex) += tex
+      elementBindings(vex) += tex
     }
 
     mapping.foreach {
@@ -145,7 +150,7 @@ package object dataview {
         }
         getMatchedFields(aa, ba).foreach {
           case (aelt: Element, belt: Element) => onElt(aelt, belt)
-          case _ => // Ignore matching of Aggregates
+          case (t, v) => aggregateMappings += (v -> t)
         }
     }
 
@@ -155,7 +160,7 @@ package object dataview {
 
     val targetSeen: Option[mutable.Set[Data]] = if (total) Some(mutable.Set.empty[Data]) else None
 
-    val resultBindings = childBindings.map {
+    val elementResult = elementBindings.map {
       case (data, targets) =>
         val targetsx = targets match {
           case collection.Seq(target: Element) => target
@@ -183,23 +188,25 @@ package object dataview {
     }
 
     view match {
-      case elt: Element   => view.bind(ViewBinding(resultBindings(elt)))
+      case elt: Element   => view.bind(ViewBinding(elementResult(elt)))
       case agg: Aggregate =>
-        // We record total Data mappings to provide a better .toTarget
-        val topt = target match {
-          case d: Data if total => Some(d)
+        // Don't forget the potential mapping of the view to the target!
+        target match {
+          case d: Data if total =>
+            aggregateMappings += (agg -> d)
           case _ =>
-            // Record views that don't have the simpler .toTarget for later renaming
-            Builder.unnamedViews += view
-            None
         }
-        // TODO We must also record children as unnamed, some could be namable but this requires changes to the Binding
+
+        val fullResult = elementResult ++ aggregateMappings
+
+        // We need to record any Aggregates that don't have a 1-1 mapping (including the view
+        // itself)
         getRecursiveFields.lazily(view, "_").foreach {
-          case (agg: Aggregate, _) if agg != view =>
-            Builder.unnamedViews += agg
+          case (unnamed: Aggregate, _) if !fullResult.contains(unnamed) =>
+            Builder.unnamedViews += unnamed
           case _ => // Do nothing
         }
-        agg.bind(AggregateViewBinding(resultBindings, topt))
+        agg.bind(AggregateViewBinding(fullResult))
     }
   }
 
@@ -208,8 +215,8 @@ package object dataview {
   private def unfoldView(elt: Element): LazyList[Element] = {
     def rec(e: Element): LazyList[Element] = e.topBindingOpt match {
       case Some(ViewBinding(target)) => target #:: rec(target)
-      case Some(AggregateViewBinding(mapping, _)) =>
-        val target = mapping(e)
+      case Some(avb: AggregateViewBinding) =>
+        val target = avb.lookup(e).get
         target #:: rec(target)
       case Some(_) | None => LazyList.empty
     }
@@ -246,15 +253,11 @@ package object dataview {
     */
   private[chisel3] def reifySingleData(data: Data): Option[Data] = {
     val candidate: Option[Data] =
-      data.binding.collect { // First check if this is a total mapping of an Aggregate
-        case AggregateViewBinding(_, Some(t)) => t
-      }.orElse { // Otherwise look via top binding
-        data.topBindingOpt match {
-          case None                                  => None
-          case Some(ViewBinding(target))             => Some(target)
-          case Some(AggregateViewBinding(lookup, _)) => lookup.get(data)
-          case Some(_)                               => None
-        }
+      data.topBindingOpt match {
+        case None                               => None
+        case Some(ViewBinding(target))          => Some(target)
+        case Some(AggregateViewBinding(lookup)) => lookup.get(data)
+        case Some(_)                            => None
       }
     candidate.flatMap { d =>
       // Candidate may itself be a view, keep tracing in those cases

core/src/main/scala/chisel3/experimental/hierarchy/Lookupable.scala

@@ -173,12 +173,12 @@ object Lookupable {
     // We have to lookup the target(s) of the view since they may need to be underlying into the current context
     val newBinding = data.topBinding match {
       case ViewBinding(target) => ViewBinding(lookupData(reify(target)))
-      case avb @ AggregateViewBinding(map, targetOpt) =>
+      case avb @ AggregateViewBinding(map) =>
         data match {
-          case _: Element   => ViewBinding(lookupData(reify(map(data))))
+          case e: Element   => ViewBinding(lookupData(reify(avb.lookup(e).get)))
           case _: Aggregate =>
             // Provide a 1:1 mapping if possible
-            val singleTargetOpt = targetOpt.filter(_ => avb == data.binding.get).flatMap(reifySingleData)
+            val singleTargetOpt = map.get(data).filter(_ => avb == data.binding.get).flatMap(reifySingleData)
             singleTargetOpt match {
               case Some(singleTarget) => // It is 1:1!
                 // This is a little tricky because the values in newMap need to point to Elements of newTarget
@@ -187,15 +187,15 @@ object Lookupable {
                   case (res, from) =>
                     (res: Data) -> mapRootAndExtractSubField(map(from), _ => newTarget)
                 }.toMap
-                AggregateViewBinding(newMap, Some(newTarget))
+                AggregateViewBinding(newMap + (result -> newTarget))
 
               case None => // No 1:1 mapping so we have to do a flat binding
                 // Just remap each Element of this aggregate
                 val newMap = coiterate(result, data).map {
                   // Upcast res to Data since Maps are invariant in the Key type parameter
-                  case (res, from) => (res: Data) -> lookupData(reify(map(from)))
+                  case (res, from) => (res: Data) -> lookupData(reify(avb.lookup(from).get))
                 }.toMap
-                AggregateViewBinding(newMap, None)
+                AggregateViewBinding(newMap)
             }
         }
     }
@@ -204,8 +204,8 @@ object Lookupable {
     // We must also mark non-1:1 and child Aggregates in the view for renaming
     newBinding match {
       case _: ViewBinding => // Do nothing
-      case AggregateViewBinding(_, target) =>
-        if (target.isEmpty) {
+      case AggregateViewBinding(childMap) =>
+        if (!childMap.contains(result)) {
           Builder.unnamedViews += result
         }
         // Binding does not capture 1:1 for child aggregates views

core/src/main/scala/chisel3/experimental/package.scala

@@ -57,6 +57,34 @@ package object experimental {
   type Direction = ActualDirection
   val Direction = ActualDirection
 
+  /** The same as [[IO]] except there is no prefix for the name of the val */
+  def FlatIO[T <: Record](gen: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = noPrefix {
+    import dataview._
+    def coerceDirection(d: Data) = {
+      import chisel3.{SpecifiedDirection => SD}
+      DataMirror.specifiedDirectionOf(gen) match {
+        case SD.Flip   => Flipped(d)
+        case SD.Input  => Input(d)
+        case SD.Output => Output(d)
+        case _         => d
+      }
+    }
+    val ports: Seq[Data] =
+      gen.elements.toSeq.reverse.map {
+        case (name, data) =>
+          val p = IO(coerceDirection(chiselTypeClone(data).asInstanceOf[Data]))
+          p.suggestName(name)
+          p
+
+      }
+
+    implicit val dv: DataView[Seq[Data], T] = DataView.mapping(
+      _ => chiselTypeClone(gen).asInstanceOf[T],
+      (seq, rec) => seq.zip(rec.elements.toSeq.reverse).map { case (port, (_, field)) => port -> field }
+    )
+    ports.viewAs[T]
+  }
+
   implicit class ChiselRange(val sc: StringContext) extends AnyVal {
 
     import scala.language.experimental.macros

core/src/main/scala/chisel3/internal/BiConnect.scala

@@ -285,7 +285,13 @@ private[chisel3] object BiConnect {
       case _ => true
     }
 
-    typeCheck && contextCheck && bindingCheck && flow_check && sourceNotLiteralCheck
+    // do not bulk connect the 'io' pseudo-bundle of a BlackBox since it will be decomposed in FIRRTL
+    def blackBoxCheck = Seq(source, sink).map(_._parent).forall {
+      case Some(_: BlackBox) => false
+      case _ => true
+    }
+
+    typeCheck && contextCheck && bindingCheck && flow_check && sourceNotLiteralCheck && blackBoxCheck
   }
 
   // These functions (finally) issue the connection operation