@@ -21,7 +21,14 @@ systemic name-stability issues, please refer to the naming [cookbook](../cookboo
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// Imports used by the following examples
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import chisel3 ._
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import chisel3 .experimental .{prefix , noPrefix }
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+ ```
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+
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+ ``` scala mdoc:invisible
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import circt .stage .ChiselStage
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+ def emitSystemVerilog (gen : => RawModule ): String = {
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+ val prettyArgs = Array (" --disable-all-randomization" , " --strip-debug-info" )
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+ ChiselStage .emitSystemVerilog(gen, firtoolOpts = prettyArgs)
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+ }
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```
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With the release of Chisel 3.5, users are required to add the following line to
@@ -51,7 +58,7 @@ class Example1 extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new Example1 )
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+ emitSystemVerilog(new Example1 )
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```
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Otherwise, it is rewritten to also include the name as a prefix to any signals generated while executing the right-hand-
@@ -75,7 +82,7 @@ class Example2 extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new Example2 )
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+ emitSystemVerilog(new Example2 )
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```
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Prefixing can also be derived from the name of signals on the left-hand side of a connection.
@@ -98,7 +105,7 @@ class ConnectPrefixing extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new ConnectPrefixing )
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+ emitSystemVerilog(new ConnectPrefixing )
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```
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Note that the naming also works if the hardware type is nested in an ` Option ` or a subtype of ` Iterable ` :
@@ -109,19 +116,22 @@ class Example3 extends Module {
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// val in = autoNameRecursively("in")(prefix("in")(IO(Input(UInt(2.W)))))
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val out = IO (Output (UInt ()))
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- // val out = autoNameRecursively("out")(prefix("out")(IO(Output(UInt(2.W )))))
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+ // val out = autoNameRecursively("out")(prefix("out")(IO(Output(UInt()))))
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- def inXin () = in * in
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+ def func () = {
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+ val delay = RegNext (in)
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+ delay + 1 .U
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+ }
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- val opt = Some (3 . U + inXin ())
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- // Note that the intermediate result of the inXin () is prefixed with `opt`:
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- // val opt = autoNameRecursively("opt")(prefix("opt")(Some(3.U + inXin() )))
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+ val opt = Some (func ())
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+ // Note that the register in func () is prefixed with `opt`:
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+ // val opt = autoNameRecursively("opt")(prefix("opt")(Some(func( )))
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out := opt.get + 1 .U
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new Example3 )
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+ emitSystemVerilog(new Example3 )
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```
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There is also a slight variant (` autoNameRecursivelyProduct ` ) for naming hardware with names provided by an unapply:
@@ -135,7 +145,7 @@ class UnapplyExample extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new UnapplyExample )
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+ emitSystemVerilog(new UnapplyExample )
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```
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Note that the compiler plugin will not insert a prefix in these cases because it is ambiguous what the prefix should be.
@@ -169,8 +179,8 @@ class Example5 extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new Example4 )
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- ChiselStage . emitSystemVerilog(new Example5 )
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+ emitSystemVerilog(new Example4 )
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+ emitSystemVerilog(new Example5 )
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```
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Also note that the prefixes append to each other (including the prefix generated by the compiler plugin):
@@ -186,7 +196,7 @@ class Example6 extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new Example6 )
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+ emitSystemVerilog(new Example6 )
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```
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Sometimes you may want to disable the prefixing. This might occur if you are writing a library function and
@@ -203,7 +213,7 @@ class Example7 extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new Example7 )
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+ emitSystemVerilog(new Example7 )
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```
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### Suggest a Signal's Name (or the instance name of a Module)
@@ -222,7 +232,7 @@ class Example8 extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new Example8 )
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+ emitSystemVerilog(new Example8 )
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```
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Note that using ` .suggestName ` does ** not** affect prefixes derived from val names;
@@ -265,7 +275,7 @@ class ConnectionPrefixExample extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new ConnectionPrefixExample )
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+ emitSystemVerilog(new ConnectionPrefixExample )
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```
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As this example illustrates, this behavior is slightly inconsistent so is subject to change in a future version of Chisel.
@@ -291,7 +301,7 @@ class TemporaryExample extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new TemporaryExample )
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+ emitSystemVerilog(new TemporaryExample )
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```
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If an unnamed signal is itself used to generate a prefix, the leading ` _ ` will be ignored to avoid double ` __ ` in the names of further nested signals.
@@ -311,7 +321,7 @@ class TemporaryPrefixExample extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new TemporaryPrefixExample )
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+ emitSystemVerilog(new TemporaryPrefixExample )
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```
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@@ -333,8 +343,8 @@ class Example9(width: Int) extends Module {
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}
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```
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``` scala mdoc:verilog
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- ChiselStage . emitSystemVerilog(new Example9 (8 ))
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- ChiselStage . emitSystemVerilog(new Example9 (1 ))
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+ emitSystemVerilog(new Example9 (8 ))
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+ emitSystemVerilog(new Example9 (1 ))
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```
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### Reflection Naming
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