Merge branch 'master' into release

Author: ucbjrl

chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala

@@ -362,7 +362,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
   * Record should only be extended by libraries and fairly sophisticated generators.
   * RTL writers should use [[Bundle]].  See [[Record#elements]] for an example.
   */
-abstract class Record extends Aggregate {
+abstract class Record(private[chisel3] implicit val compileOptions: CompileOptions) extends Aggregate {
 
   /** The collection of [[Data]]
     *
@@ -464,7 +464,7 @@ abstract class Record extends Aggregate {
   *   }
   * }}}
   */
-class Bundle extends Record {
+class Bundle(implicit compileOptions: CompileOptions) extends Record {
   override def className = "Bundle"
 
   /** The collection of [[Data]]

chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala

@@ -80,35 +80,50 @@ object BiConnect {
           }
         }
       }
-      // Handle Record case
-      case (left_r: Record, right_r: Record) => {
-        // Verify right has no extra fields that left doesn't have
-        for((field, right_sub) <- right_r.elements) {
-          if(!left_r.elements.isDefinedAt(field)) {
-            if (connectCompileOptions.connectFieldsMustMatch) {
-              throw MissingLeftFieldException(field)
-            }
-          }
+      // Handle Records defined in Chisel._ code (change to NotStrict)
+      case (left_r: Record, right_r: Record) => (left_r.compileOptions, right_r.compileOptions) match {
+        case (ExplicitCompileOptions.NotStrict, _) =>
+          left_r.bulkConnect(right_r)(sourceInfo, ExplicitCompileOptions.NotStrict)
+        case (_, ExplicitCompileOptions.NotStrict) =>
+          left_r.bulkConnect(right_r)(sourceInfo, ExplicitCompileOptions.NotStrict)
+        case _ => recordConnect(sourceInfo, connectCompileOptions, left_r, right_r, context_mod)
+      }
+
+      // Left and right are different subtypes of Data so fail
+      case (left, right) => throw MismatchedException(left.toString, right.toString)
+    }
+
+  // Do connection of two Records
+  def recordConnect(sourceInfo: SourceInfo,
+                    connectCompileOptions: CompileOptions,
+                    left_r: Record,
+                    right_r: Record,
+                    context_mod: UserModule): Unit = {
+    // Verify right has no extra fields that left doesn't have
+    for((field, right_sub) <- right_r.elements) {
+      if(!left_r.elements.isDefinedAt(field)) {
+        if (connectCompileOptions.connectFieldsMustMatch) {
+          throw MissingLeftFieldException(field)
         }
-        // For each field in left, descend with right
-        for((field, left_sub) <- left_r.elements) {
-          try {
-            right_r.elements.get(field) match {
-              case Some(right_sub) => connect(sourceInfo, connectCompileOptions, left_sub, right_sub, context_mod)
-              case None => {
-                if (connectCompileOptions.connectFieldsMustMatch) {
-                  throw MissingRightFieldException(field)
-                }
-              }
+      }
+    }
+    // For each field in left, descend with right
+    for((field, left_sub) <- left_r.elements) {
+      try {
+        right_r.elements.get(field) match {
+          case Some(right_sub) => connect(sourceInfo, connectCompileOptions, left_sub, right_sub, context_mod)
+          case None => {
+            if (connectCompileOptions.connectFieldsMustMatch) {
+              throw MissingRightFieldException(field)
             }
-          } catch {
-            case BiConnectException(message) => throw BiConnectException(s".$field$message")
           }
         }
+      } catch {
+        case BiConnectException(message) => throw BiConnectException(s".$field$message")
       }
-      // Left and right are different subtypes of Data so fail
-      case (left, right) => throw MismatchedException(left.toString, right.toString)
     }
+  }
+
 
   // These functions (finally) issue the connection operation
   // Issue with right as sink, left as source

chiselFrontend/src/main/scala/chisel3/core/Bits.scala

@@ -594,8 +594,11 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
     binop(sourceInfo, SInt(this.width), RemOp, that)
 
   final def * (that: UInt): SInt = macro SourceInfoTransform.thatArg
-  def do_* (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt =
-    binop(sourceInfo, SInt(this.width + that.width), TimesOp, that)
+  def do_* (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = {
+    val thatToSInt = that.zext()
+    val result = binop(sourceInfo, SInt(this.width + thatToSInt.width), TimesOp, thatToSInt)
+    result.tail(1).asSInt
+  }
 
   /** add (width +1) operator */
   final def +& (that: SInt): SInt = macro SourceInfoTransform.thatArg

chiselFrontend/src/main/scala/chisel3/core/Module.scala

@@ -32,7 +32,10 @@ object Module {
 
     val parent = Builder.currentModule
     val whenDepth: Int = Builder.whenDepth
+
+    // Save then clear clock and reset to prevent leaking scope, must be set again in the Module
     val clockAndReset: Option[ClockAndReset] = Builder.currentClockAndReset
+    Builder.currentClockAndReset = None
 
     // Execute the module, this has the following side effects:
     //   - set currentModule
@@ -108,7 +111,7 @@ abstract class BaseModule extends HasId {
     require(_closed, "Can't get ports before module close")
     _ports.toSeq
   }
-  
+
   // These methods allow checking some properties of ports before the module is closed,
   // mainly for compatibility purposes.
   protected def portsContains(elem: Data): Boolean = _ports contains elem

chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala

@@ -55,15 +55,31 @@ object MonoConnect {
   * during the recursive decent and then rethrow them with extra information added.
   * This gives the user a 'path' to where in the connections things went wrong.
   */
-  def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Data, source: Data, context_mod: UserModule): Unit =
+  //scalastyle:off cyclomatic.complexity method.length
+  def connect(
+      sourceInfo: SourceInfo,
+      connectCompileOptions: CompileOptions,
+      sink: Data,
+      source: Data,
+      context_mod: UserModule): Unit =
     (sink, source) match {
-      // Handle element case (root case)
-      case (sink_e: Element, source_e: Element) => {
+
+      // Handle legal element cases, note (Bool, Bool) is caught by the first two, as Bool is a UInt
+      case (sink_e: Bool, source_e: UInt) =>
         elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
-        // TODO(twigg): Verify the element-level classes are connectable
-      }
+      case (sink_e: UInt, source_e: Bool) =>
+        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+      case (sink_e: UInt, source_e: UInt) =>
+        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+      case (sink_e: SInt, source_e: SInt) =>
+        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+      case (sink_e: FixedPoint, source_e: FixedPoint) =>
+        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+      case (sink_e: Clock, source_e: Clock) =>
+        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+
       // Handle Vec case
-      case (sink_v: Vec[Data @unchecked], source_v: Vec[Data @unchecked]) => {
+      case (sink_v: Vec[Data @unchecked], source_v: Vec[Data @unchecked]) =>
         if(sink_v.length != source_v.length) { throw MismatchedVecException }
         for(idx <- 0 until sink_v.length) {
           try {
@@ -73,9 +89,9 @@ object MonoConnect {
             case MonoConnectException(message) => throw MonoConnectException(s"($idx)$message")
           }
         }
-      }
+
       // Handle Record case
-      case (sink_r: Record, source_r: Record) => {
+      case (sink_r: Record, source_r: Record) =>
         // For each field, descend with right
         for((field, sink_sub) <- sink_r.elements) {
           try {
@@ -91,7 +107,7 @@ object MonoConnect {
             case MonoConnectException(message) => throw MonoConnectException(s".$field$message")
           }
         }
-      }
+
       // Sink and source are different subtypes of data so fail
       case (sink, source) => throw MismatchedException(sink.toString, source.toString)
     }

src/main/resources/Makefile renamed to src/main/resources/chisel3/Makefile

@@ -28,7 +28,7 @@ object TesterDriver extends BackendCompilationUtilities {
 
     // Copy CPP harness and other Verilog sources from resources into files
     val cppHarness =  new File(path, "top.cpp")
-    copyResourceToFile("/top.cpp", cppHarness)
+    copyResourceToFile("/chisel3/top.cpp", cppHarness)
     val additionalVFiles = additionalVResources.map((name: String) => {
       val mangledResourceName = name.replace("/", "_")
       val out = new File(path, mangledResourceName)

src/main/resources/top.cpp renamed to src/main/resources/chisel3/top.cpp

@@ -126,10 +126,10 @@ class AnalogIntegrationTester(mod: => AnalogDUTModule) extends BasicTester {
 class AnalogIntegrationSpec extends ChiselFlatSpec {
   behavior of "Verilator"
   it should "support simple bidirectional wires" in {
-    assertTesterPasses(new AnalogIntegrationTester(new AnalogSmallDUT), Seq("/AnalogBlackBox.v"))
+    assertTesterPasses(new AnalogIntegrationTester(new AnalogSmallDUT), Seq("/chisel3/AnalogBlackBox.v"))
   }
   // Use this test once Verilator supports alias
   ignore should "support arbitrary bidirectional wires" in {
-    assertTesterPasses(new AnalogIntegrationTester(new AnalogDUT), Seq("/AnalogBlackBox.v"))
+    assertTesterPasses(new AnalogIntegrationTester(new AnalogDUT), Seq("/chisel3/AnalogBlackBox.v"))
   }
 }

src/main/scala/chisel3/testers/TesterDriver.scala

@@ -130,7 +130,7 @@ class AnalogSpec extends ChiselFlatSpec {
       val mod = Module(new AnalogReaderBlackBox)
       mod.io.bus <> writer.io.bus
       check(mod)
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "error if any bulk connected more than once" in {
@@ -149,7 +149,7 @@ class AnalogSpec extends ChiselFlatSpec {
       val mods = Seq.fill(2)(Module(new AnalogReaderBlackBox))
       attach(writer.io.bus, mods(0).io.bus, mods(1).io.bus)
       mods.foreach(check(_))
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "work with 3 blackboxes separately attached via a wire" in {
@@ -160,7 +160,7 @@ class AnalogSpec extends ChiselFlatSpec {
       attach(busWire, mods(0).io.bus)
       attach(mods(1).io.bus, busWire)
       mods.foreach(check(_))
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   // This does not currently work in Verilator unless Firrtl does constant prop and dead code
@@ -173,7 +173,7 @@ class AnalogSpec extends ChiselFlatSpec {
       attach(busWire(1), mod.io.bus)
       attach(busWire(0), busWire(1))
       check(mod)
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "work with blackboxes at different levels of the module hierarchy" in {
@@ -182,7 +182,7 @@ class AnalogSpec extends ChiselFlatSpec {
       val busWire = Wire(writer.io.bus)
       attach(writer.io.bus, mods(0).io.bus, mods(1).io.bus)
       mods.foreach(check(_))
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   // This does not currently work in Verilator, but does work in VCS
@@ -193,7 +193,7 @@ class AnalogSpec extends ChiselFlatSpec {
       connector.io.bus1 <> writer.io.bus
       reader.io.bus <> connector.io.bus2
       check(reader)
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "NOT support conditional connection of analog types" in {
@@ -204,7 +204,7 @@ class AnalogSpec extends ChiselFlatSpec {
           mod.io.bus <> writer.io.bus
         }
         check(mod)
-      }, Seq("/AnalogBlackBox.v"))
+      }, Seq("/chisel3/AnalogBlackBox.v"))
     }
   }
 }

src/test/resources/AnalogBlackBox.v renamed to src/test/resources/chisel3/AnalogBlackBox.v

@@ -138,18 +138,18 @@ class BlackBoxWithParamsTester extends BasicTester {
 class BlackBoxSpec extends ChiselFlatSpec {
   "A BlackBoxed inverter" should "work" in {
     assertTesterPasses({ new BlackBoxTester },
-        Seq("/BlackBoxTest.v"))
+        Seq("/chisel3/BlackBoxTest.v"))
   }
   "Multiple BlackBoxes" should "work" in {
     assertTesterPasses({ new MultiBlackBoxTester },
-        Seq("/BlackBoxTest.v"))
+        Seq("/chisel3/BlackBoxTest.v"))
   }
   "A BlackBoxed register" should "work" in {
     assertTesterPasses({ new BlackBoxWithClockTester },
-        Seq("/BlackBoxTest.v"))
+        Seq("/chisel3/BlackBoxTest.v"))
   }
   "BlackBoxes with parameters" should "work" in {
     assertTesterPasses({ new BlackBoxWithParamsTester },
-        Seq("/BlackBoxTest.v"))
+        Seq("/chisel3/BlackBoxTest.v"))
   }
 }

src/test/resources/BlackBoxTest.v renamed to src/test/resources/chisel3/BlackBoxTest.v

@@ -47,7 +47,7 @@ class BlackBoxMinus extends HasBlackBoxResource {
     val in2 = Input(UInt(16.W))
     val out = Output(UInt(16.W))
   })
-  setResource("/BlackBoxTest.v")
+  setResource("/chisel3/BlackBoxTest.v")
 }
 
 class UsesBlackBoxMinusViaResource extends Module {