Implement typeName API for stable Module names (backport #3130) (#4145)

* Implement typeName API for stable Module names (#3130)

* Implement `typeName` API for a few `Data` types

* Fix silly compilation error

* Implement typeName API further for most data types and modules which need it

* Compilation error fixes

* Remove width parameter from Bool

* Test for Queue naming using typeNames

* Remove width-sensitive override for AsyncReset as it is irrelevant

* Add typeName for Analogs

* Add additional types to be tested

* Scalafmt

* Use circt ChiselStage

* Update queue naming of existing tests

* Scalafmt

* Change pipe desiredName to be consistent with other modules

* Update naming cookbook

* Update docs/src/cookbooks/naming.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/cookbooks/naming.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Add SInt to TypenameSpec

* Fix cookbook mdoc errors

* compileOnly tag on scala code

* More improvements of mdoc

* compileOnly -> compile-only

* Final mdoc review and fixes

* Add inferred UInt to test

---------

Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 0ce115e)

# Conflicts:
#	docs/src/cookbooks/naming.md
#	src/main/scala/chisel3/util/Decoupled.scala
#	src/main/scala/chisel3/util/Valid.scala

* Resolve conflicts, remove desiredName overrides, remove docs

All things that are removed can be enjoyed by users by bumping to a
newer version of Chisel.

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

core/src/main/scala/chisel3/Aggregate.scala

@@ -188,6 +188,11 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend
     }
   }
 
+  /** Give this Vec a default, stable desired name using the supplied `Data`
+    * generator's `typeName`
+    */
+  override def typeName = s"Vec${length}_${gen.typeName}"
+
   private[chisel3] override def typeEquivalent(that: Data): Boolean = that match {
     case that: Vec[T] =>
       this.length == that.length &&

core/src/main/scala/chisel3/Bits.scala

@@ -52,6 +52,11 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
 
   def cloneType: this.type = cloneTypeWidth(width)
 
+  /** A non-ambiguous name of this `Bits` instance for use in generated Verilog names
+    * Inserts the width directly after the typeName, e.g. UInt4, SInt1
+    */
+  override def typeName: String = s"${this.getClass.getSimpleName}$width"
+
   /** Tail operator
     *
     * @param n the number of bits to remove
@@ -1217,6 +1222,13 @@ sealed class AsyncReset(private[chisel3] val width: Width = Width(1)) extends El
   * @define numType $coll
   */
 sealed class Bool() extends UInt(1.W) with Reset {
+
+  /**
+    * Give this `Bool` a stable `typeName` for Verilog name generation.
+    * Specifying a Bool's width in its type name isn't necessary
+    */
+  override def typeName = "Bool"
+
   override def toString: String = {
     litToBooleanOption match {
       case Some(value) => s"Bool($value)"

core/src/main/scala/chisel3/Data.scala

@@ -805,6 +805,9 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
 
   /** Default pretty printing */
   def toPrintable: Printable
+
+  /** A non-ambiguous name of this `Data` for use in generated Verilog names */
+  def typeName: String = this.getClass.getSimpleName
 }
 
 object Data {

core/src/main/scala/chisel3/experimental/Analog.scala

@@ -39,6 +39,10 @@ final class Analog private (private[chisel3] val width: Width) extends Element {
 
   override def toString: String = stringAccessor(s"Analog$width")
 
+  /** A stable typeName for this `Analog`
+    */
+  override def typeName = s"Analog$width"
+
   private[chisel3] override def typeEquivalent(that: Data): Boolean =
     that.isInstanceOf[Analog] && this.width == that.width
 

src/main/scala/chisel3/util/Decoupled.scala

@@ -41,6 +41,11 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle {
     * @group Signals
     */
   val bits = Output(genType)
+
+  /** A stable typeName for this `ReadyValidIO` and any of its implementations
+    * using the supplied `Data` generator's `typeName`
+    */
+  override def typeName = s"${this.getClass.getSimpleName}_${gen.typeName}"
 }
 
 object ReadyValidIO {

src/main/scala/chisel3/util/Valid.scala

@@ -42,6 +42,11 @@ class Valid[+T <: Data](gen: T) extends Bundle {
     "Chisel 3.5"
   )
   def fire(dummy: Int = 0): Bool = valid
+
+  /** A non-ambiguous name of this `Valid` instance for use in generated Verilog names
+    * Inserts the parameterized generator's typeName, e.g. Valid_UInt4
+    */
+  override def typeName = s"${this.getClass.getSimpleName}_${gen.typeName}"
 }
 
 /** Factory for generating "valid" interfaces. A "valid" interface is a data-communicating interface between a producer