Make chisel3.internal.firrtl.* private (#3732)

* Width, KnownWidth, and Unknown width promoted to package chisel3
* Other classes moved to new package private chisel3.internal.firrtl.ir

Author: jackkoenig

binder/src/main/scala/PanamaCIRCTConverter.scala

@@ -13,7 +13,8 @@ import chisel3.{Data => ChiselData, _}
 import chisel3.properties.PropertyType
 import chisel3.experimental._
 import chisel3.internal._
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
+import chisel3.internal.firrtl.Converter
 import chisel3.assert.{Assert => VerifAssert}
 import chisel3.assume.{Assume => VerifAssume}
 import chisel3.cover.{Cover => VerifCover}

core/src/main/scala/chisel3/Aggregate.scala

@@ -12,7 +12,7 @@ import chisel3.experimental.{BaseModule, BundleLiteralException, HasTypeAlias, O
 import chisel3.experimental.{SourceInfo, UnlocatableSourceInfo}
 import chisel3.internal._
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.internal.sourceinfo.{SourceInfoTransform, VecTransform}
 import chisel3.reflect.DataMirror
 import _root_.firrtl.{ir => fir}

core/src/main/scala/chisel3/Bits.scala

@@ -6,14 +6,14 @@ import scala.language.experimental.macros
 import chisel3.experimental.{requireIsHardware, SourceInfo}
 import chisel3.internal.{throwException, BaseModule}
 import chisel3.internal.Builder.pushOp
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.internal.sourceinfo.{
   IntLiteralApplyTransform,
   SourceInfoTransform,
   SourceInfoWhiteboxTransform,
   UIntTransform
 }
-import chisel3.internal.firrtl.PrimOp._
+import chisel3.internal.firrtl.ir.PrimOp._
 import _root_.firrtl.{ir => firrtlir}
 import chisel3.internal.{castToInt, Builder, Warning, WarningID}
 import chisel3.util.simpleClassName

core/src/main/scala/chisel3/BlackBox.scala

@@ -5,10 +5,9 @@ package chisel3
 import chisel3.experimental.{BaseModule, Param}
 import chisel3.internal.BaseBlackBox
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.internal.throwException
 import chisel3.experimental.{SourceInfo, UnlocatableSourceInfo}
-import scala.annotation.nowarn
 
 package internal {
 
@@ -68,7 +67,6 @@ package experimental {
     * }}}
     * @note The parameters API is experimental and may change
     */
-  @nowarn("msg=class Port") // delete when Port becomes private
   abstract class ExtModule(val params: Map[String, Param] = Map.empty[String, Param]) extends BaseBlackBox {
     private[chisel3] override def generateComponent(): Option[Component] = {
       require(!_closed, "Can't generate module more than once")
@@ -126,7 +124,6 @@ package experimental {
   * }}}
   * @note The parameters API is experimental and may change
   */
-@nowarn("msg=class Port") // delete when Port becomes private
 abstract class BlackBox(
   val params: Map[String, Param] = Map.empty[String, Param])
     extends BaseBlackBox {

core/src/main/scala/chisel3/BoolFactory.scala

@@ -2,7 +2,7 @@
 
 package chisel3
 
-import chisel3.internal.firrtl.{ULit, Width}
+import chisel3.internal.firrtl.ir.ULit
 
 trait BoolFactory {
 

core/src/main/scala/chisel3/ChiselEnum.scala

@@ -8,8 +8,8 @@ import scala.reflect.macros.blackbox.Context
 import scala.collection.mutable
 import chisel3.experimental.{annotate, requireIsHardware, ChiselAnnotation, SourceInfo, UnlocatableSourceInfo}
 import chisel3.internal.Builder.pushOp
-import chisel3.internal.firrtl.PrimOp._
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir.PrimOp._
+import chisel3.internal.firrtl.ir._
 import chisel3.internal.sourceinfo._
 import chisel3.internal.{
   containsProbe,

core/src/main/scala/chisel3/Clock.scala

@@ -5,9 +5,9 @@ package chisel3
 import scala.language.experimental.macros
 import chisel3.experimental.SourceInfo
 import chisel3.internal.Builder.pushOp
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.internal.sourceinfo._
-import chisel3.internal.firrtl.PrimOp.AsUIntOp
+import chisel3.internal.firrtl.ir.PrimOp.AsUIntOp
 
 object Clock {
   def apply(): Clock = new Clock

core/src/main/scala/chisel3/Data.scala

@@ -11,7 +11,7 @@ import chisel3.experimental.dataview.reifySingleData
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal._
 import chisel3.internal.sourceinfo._
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.properties.Property
 import chisel3.reflect.DataMirror
 import chisel3.util.simpleClassName

core/src/main/scala/chisel3/Element.scala

@@ -3,7 +3,7 @@
 package chisel3
 
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.experimental.SourceInfo
 import chisel3.internal._
 

core/src/main/scala/chisel3/Layer.scala

@@ -4,7 +4,7 @@ package chisel3
 
 import chisel3.experimental.{SourceInfo, UnlocatableSourceInfo}
 import chisel3.internal.{Builder, HasId}
-import chisel3.internal.firrtl.{LayerBlockBegin, LayerBlockEnd, Node}
+import chisel3.internal.firrtl.ir.{LayerBlockBegin, LayerBlockEnd, Node}
 import chisel3.util.simpleClassName
 import scala.collection.mutable.LinkedHashSet
 

core/src/main/scala/chisel3/Mem.scala

@@ -8,7 +8,7 @@ import firrtl.{ir => fir}
 
 import chisel3.internal._
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.internal.sourceinfo.{MemTransform, SourceInfoTransform}
 import chisel3.experimental.{SourceInfo, SourceLine}
 

core/src/main/scala/chisel3/Module.scala

@@ -8,7 +8,7 @@ import scala.language.experimental.macros
 
 import chisel3.internal._
 import chisel3.internal.Builder._
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.experimental.{BaseModule, SourceInfo, UnlocatableSourceInfo}
 import chisel3.internal.sourceinfo.{InstTransform}
 import chisel3.properties.{Class, Property}
@@ -20,8 +20,6 @@ import chisel3.util.simpleClassName
 
 object Module extends SourceInfoDoc {
 
-  import scala.annotation.nowarn
-
   /** A wrapper method that all Module instantiations must be wrapped in
     * (necessary to help Chisel track internal state).
     *
@@ -32,7 +30,6 @@ object Module extends SourceInfoDoc {
   def apply[T <: BaseModule](bc: => T): T = macro InstTransform.apply[T]
 
   /** @group SourceInfoTransformMacro */
-  @nowarn("msg=class Port") // delete when Port becomes private
   def do_apply[T <: BaseModule](bc: => T)(implicit sourceInfo: SourceInfo): T = {
     // Instantiate the module definition.
     val module = evaluate[T](bc)
@@ -345,7 +342,6 @@ package internal {
 package experimental {
 
   import chisel3.experimental.hierarchy.core.{IsInstantiable, Proto}
-  import scala.annotation.nowarn
 
   object BaseModule {
     implicit class BaseModuleExtensions[T <: BaseModule](b: T)(implicit si: SourceInfo) {
@@ -366,7 +362,6 @@ package experimental {
   /** Abstract base class for Modules, an instantiable organizational unit for RTL.
     */
   // TODO: seal this?
-  @nowarn("msg=class Port") // delete when Port becomes private
   abstract class BaseModule extends HasId with IsInstantiable {
     _parent.foreach(_.addId(this))
 

core/src/main/scala/chisel3/Mux.scala

@@ -8,8 +8,8 @@ import chisel3.internal._
 import chisel3.internal.Builder.pushOp
 import chisel3.experimental.{requireIsHardware, SourceInfo}
 import chisel3.internal.sourceinfo.MuxTransform
-import chisel3.internal.firrtl._
-import chisel3.internal.firrtl.PrimOp._
+import chisel3.internal.firrtl.ir._
+import chisel3.internal.firrtl.ir.PrimOp._
 
 object Mux extends SourceInfoDoc {
 

core/src/main/scala/chisel3/Printable.scala

@@ -2,7 +2,7 @@
 
 package chisel3
 
-import chisel3.internal.firrtl.Component
+import chisel3.internal.firrtl.ir.Component
 
 import scala.collection.mutable
 

core/src/main/scala/chisel3/Printf.scala

@@ -162,7 +162,7 @@ object printf {
 
     Printable.checkScope(pable)
 
-    pushCommand(chisel3.internal.firrtl.Printf(printfId, sourceInfo, clock.ref, pable))
+    pushCommand(chisel3.internal.firrtl.ir.Printf(printfId, sourceInfo, clock.ref, pable))
     printfId
   }
   private[chisel3] def printfWithoutReset(

core/src/main/scala/chisel3/RawModule.scala

@@ -4,13 +4,12 @@ package chisel3
 
 import scala.util.Try
 import scala.language.experimental.macros
-import scala.annotation.nowarn
 import chisel3.experimental.{BaseModule, SourceInfo, UnlocatableSourceInfo}
 import chisel3.internal._
 import chisel3.experimental.hierarchy.{InstanceClone, ModuleClone}
 import chisel3.properties.{DynamicObject, StaticObject}
 import chisel3.internal.Builder._
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import _root_.firrtl.annotations.{IsModule, ModuleTarget}
 import scala.collection.immutable.VectorBuilder
 import scala.collection.mutable.ArrayBuffer
@@ -19,7 +18,6 @@ import scala.collection.mutable.ArrayBuffer
   * This abstract base class is a user-defined module which does not include implicit clock and reset and supports
   * multiple IO() declarations.
   */
-@nowarn("msg=class Port") // delete when Port becomes private
 abstract class RawModule extends BaseModule {
 
   /** Hook to invoke hardware generators after the rest of the Module is constructed.
@@ -102,7 +100,7 @@ abstract class RawModule extends BaseModule {
   //
   // Other Internal Functions
   //
-  private var _firrtlPorts: Option[Seq[firrtl.Port]] = None
+  private var _firrtlPorts: Option[Seq[Port]] = None
 
   private[chisel3] def checkPorts(): Unit = {
     for ((port, source) <- getModulePortsAndLocators) {

core/src/main/scala/chisel3/Reg.scala

@@ -6,7 +6,7 @@ import scala.language.experimental.macros
 
 import chisel3.internal._
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.experimental.SourceInfo
 import chisel3.internal.sourceinfo.SourceInfoTransform
 

core/src/main/scala/chisel3/SIntFactory.scala

@@ -2,7 +2,7 @@
 
 package chisel3
 
-import chisel3.internal.firrtl.{SLit, Width}
+import chisel3.internal.firrtl.ir.SLit
 
 trait SIntFactory {
 

core/src/main/scala/chisel3/UIntFactory.scala

@@ -2,7 +2,7 @@
 
 package chisel3
 
-import chisel3.internal.firrtl.{KnownWidth, ULit, UnknownWidth, Width}
+import chisel3.internal.firrtl.ir.ULit
 import firrtl.Utils
 
 // This is currently a factory because both Bits and UInt inherit it.

core/src/main/scala/chisel3/VerificationStatement.scala

@@ -6,7 +6,7 @@ import scala.reflect.macros.blackbox.Context
 import scala.language.experimental.macros
 import chisel3.internal._
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.experimental.SourceInfo
 
 import scala.annotation.nowarn

core/src/main/scala/chisel3/When.scala

@@ -5,7 +5,7 @@ package chisel3
 import scala.language.experimental.macros
 import chisel3.internal._
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 import chisel3.experimental.{SourceInfo, UnlocatableSourceInfo}
 
 object when {

core/src/main/scala/chisel3/Width.scala

@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chisel3
+
+object Width {
+  def apply(x: Int): Width = KnownWidth(x)
+  def apply(): Width = UnknownWidth()
+}
+
+sealed abstract class Width {
+  type W = Int
+  def min(that:              Width): Width = this.op(that, _ min _)
+  def max(that:              Width): Width = this.op(that, _ max _)
+  def +(that:                Width): Width = this.op(that, _ + _)
+  def +(that:                Int):   Width = this.op(this, (a, b) => a + that)
+  def shiftRight(that:       Int): Width = this.op(this, (a, b) => 0.max(a - that))
+  def dynamicShiftLeft(that: Width): Width =
+    this.op(that, (a, b) => a + (1 << b) - 1)
+
+  def known: Boolean
+  def get:   W
+  protected def op(that: Width, f: (W, W) => W): Width
+}
+
+sealed case class UnknownWidth() extends Width {
+  def known: Boolean = false
+  def get:   Int = None.get
+  def op(that: Width, f: (W, W) => W): Width = this
+  override def toString: String = ""
+}
+
+sealed case class KnownWidth(value: Int) extends Width {
+  require(value >= 0)
+  def known: Boolean = true
+  def get:   Int = value
+  def op(that: Width, f: (W, W) => W): Width = that match {
+    case KnownWidth(x) => KnownWidth(f(value, x))
+    case _             => that
+  }
+  override def toString: String = s"<${value.toString}>"
+}

core/src/main/scala/chisel3/aop/Aspect.scala

@@ -41,7 +41,7 @@ object Aspect {
     * @param chiselIR
     * @return
     */
-  def getFirrtl(chiselIR: chisel3.internal.firrtl.Circuit): firrtl.ir.Circuit = {
+  def getFirrtl(chiselIR: chisel3.internal.firrtl.ir.Circuit): firrtl.ir.Circuit = {
     chisel3.internal.firrtl.Converter.convert(chiselIR)
   }
 }

core/src/main/scala/chisel3/connectable/Connection.scala

@@ -5,7 +5,7 @@ package chisel3.connectable
 import chisel3.{Aggregate, BiConnectException, Data, DontCare, InternalErrorException, RawModule}
 import chisel3.internal.{BiConnect, Builder}
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl.DefInvalid
+import chisel3.internal.firrtl.ir.DefInvalid
 import chisel3.experimental.{prefix, SourceInfo, UnlocatableSourceInfo}
 import chisel3.experimental.{attach, Analog}
 import chisel3.reflect.DataMirror.hasProbeTypeModifier

core/src/main/scala/chisel3/experimental/Analog.scala

@@ -2,9 +2,8 @@
 
 package chisel3.experimental
 
-import chisel3.internal.firrtl.Width
 import chisel3.internal._
-import chisel3.{ActualDirection, Bits, Data, Element, PString, Printable, RawModule, SpecifiedDirection, UInt}
+import chisel3.{ActualDirection, Bits, Data, Element, PString, Printable, RawModule, SpecifiedDirection, UInt, Width}
 
 import scala.collection.mutable
 

core/src/main/scala/chisel3/experimental/Attach.scala

@@ -5,7 +5,7 @@ package chisel3.experimental
 import chisel3.{ChiselException, RawModule}
 import chisel3.internal._
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.ir._
 
 object attach {
   // Exceptions that can be generated by attach

core/src/main/scala/chisel3/experimental/IntrinsicModule.scala

@@ -5,14 +5,12 @@ package chisel3.experimental
 import chisel3.SpecifiedDirection
 import chisel3.experimental.{BaseModule, Param}
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl._
-import scala.annotation.nowarn
+import chisel3.internal.firrtl.ir._
 
 private[chisel3] abstract class BaseIntrinsicModule(intrinsicName: String) extends BaseModule {
   val intrinsic = intrinsicName
 }
 
-@nowarn("msg=class Port") // delete when Port becomes private
 abstract class IntrinsicModule(intrinsicName: String, val params: Map[String, Param] = Map.empty[String, Param])
     extends BaseIntrinsicModule(intrinsicName) {
   private[chisel3] override def generateComponent(): Option[Component] = {

core/src/main/scala/chisel3/experimental/OpaqueType.scala

@@ -4,7 +4,7 @@ package chisel3.experimental
 
 import chisel3._
 import chisel3.internal.{Builder, ChildBinding}
-import chisel3.internal.firrtl.Arg
+import chisel3.internal.firrtl.ir.Arg
 
 /** Indicates if this Record represents an "Opaque Type"
   *

core/src/main/scala/chisel3/experimental/hierarchy/DefinitionClone.scala

@@ -4,7 +4,7 @@ package chisel3.experimental.hierarchy
 
 import chisel3.experimental.BaseModule
 import chisel3.internal.{HasId, PseudoModule}
-import chisel3.internal.firrtl.{Component, Ref}
+import chisel3.internal.firrtl.ir.{Component, Ref}
 
 /** Represents a Definition root module, when accessing something from a definition
   *