make SRAM targets accessible from SRAMInterface (#3728)

Author: debs-sifive

core/src/main/scala/chisel3/package.scala

@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: Apache-2.0
 
-import firrtl.annotations.{IsMember, Named}
-import chisel3.internal.ExceptionHelpers
+import firrtl.annotations.{IsMember, Named, ReferenceTarget}
+import chisel3.internal.{ExceptionHelpers, NamedComponent}
+import chisel3.experimental.BaseModule
 
 import java.util.{MissingFormatArgumentException, UnknownFormatConversionException}
 import scala.collection.mutable
@@ -412,4 +413,25 @@ package object chisel3 {
     "this feature will not be supported as part of the migration to the MLIR-based FIRRTL Compiler (MFC). For more information about this migration, please see the Chisel ROADMAP.md."
 
   final val deprecatedPublicAPIMsg = "APIs in chisel3.internal are not intended to be public"
+
+  /** Contains universal methods for target accesses.
+    */
+  sealed trait HasTarget {
+    def toTarget:         ReferenceTarget
+    def toAbsoluteTarget: ReferenceTarget
+    def toRelativeTarget(root: Option[BaseModule]): ReferenceTarget
+  }
+
+  object HasTarget {
+
+    /** This wrapping hides the actual object, ensuring users only have access
+      * to the target methods (instead of the type of the underlying object).
+      */
+    private[chisel3] def apply(t: NamedComponent): HasTarget = new HasTarget {
+      def toTarget = t.toTarget
+      def toAbsoluteTarget = t.toAbsoluteTarget
+      def toRelativeTarget(root: Option[BaseModule]) = t.toRelativeTarget(root)
+    }
+
+  }
 }

src/main/scala/chisel3/util/SRAM.scala

@@ -79,6 +79,7 @@ class MemoryReadWritePort[T <: Data](tpe: T, addrWidth: Int, masked: Boolean) ex
   * @param numReadPorts The number of read ports
   * @param numWritePorts The number of write ports
   * @param numReadwritePorts The number of read/write ports
+  * @param masked Whether the memory is write masked
   */
 class SRAMInterface[T <: Data](
   memSize:           BigInt,
@@ -104,6 +105,11 @@ class SRAMInterface[T <: Data](
   val writePorts: Vec[MemoryWritePort[T]] = Vec(numWritePorts, new MemoryWritePort(tpe, addrWidth, masked))
   val readwritePorts: Vec[MemoryReadWritePort[T]] =
     Vec(numReadwritePorts, new MemoryReadWritePort(tpe, addrWidth, masked))
+
+  private[chisel3] var _underlying: Option[HasTarget] = None
+
+  /** Target information for annotating the underlying SRAM if it is known. */
+  def underlying: Option[HasTarget] = _underlying
 }
 
 /** A memory file with which to preload an [[SRAM]]
@@ -459,8 +465,9 @@ object SRAM {
       )
     }
 
-    val _out = Wire(new SRAMInterface(size, tpe, numReadPorts, numWritePorts, numReadwritePorts, isVecMem))
     val mem = SyncReadMem(size, tpe)
+    val _out = Wire(new SRAMInterface(size, tpe, numReadPorts, numWritePorts, numReadwritePorts, isVecMem))
+    _out._underlying = Some(HasTarget(mem))
 
     for ((clock, port) <- readPortClocks.zip(_out.readPorts)) {
       port.data := mem.read(port.address, port.enable, clock)

src/test/scala/chiselTests/util/SRAMSpec.scala

@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util
+
+import chisel3._
+import chisel3.util.SRAM
+import chisel3.experimental.{annotate, ChiselAnnotation}
+import chiselTests.ChiselFlatSpec
+import _root_.circt.stage.ChiselStage.emitCHIRRTL
+import firrtl.annotations.{Annotation, ReferenceTarget, SingleTargetAnnotation}
+
+class SRAMSpec extends ChiselFlatSpec {
+  case class DummyAnno(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] {
+    override def duplicate(n: ReferenceTarget) = this.copy(target = n)
+  }
+  behavior.of("SRAMInterface")
+
+  it should "Provide target information about its instantiating SRAM" in {
+
+    class Top extends Module {
+      val sram = SRAM(
+        size = 32,
+        tpe = UInt(8.W),
+        numReadPorts = 0,
+        numWritePorts = 0,
+        numReadwritePorts = 1
+      )
+      require(sram.underlying.nonEmpty)
+      annotate(new ChiselAnnotation {
+        override def toFirrtl: Annotation = DummyAnno(sram.underlying.get.toTarget)
+      })
+    }
+    val (chirrtlCircuit, annos) = getFirrtlAndAnnos(new Top)
+    val chirrtl = chirrtlCircuit.serialize
+    chirrtl should include("module Top :")
+    chirrtl should include("smem sram_mem : UInt<8> [32]")
+    chirrtl should include(
+      "wire sram : { readPorts : { flip address : UInt<6>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1]}"
+    )
+
+    val dummyAnno = annos.collectFirst { case DummyAnno(t) => (t.toString) }
+    dummyAnno should be(Some("~Top|Top>sram_mem"))
+  }
+
+}