Bump for 091719-SNAPSHOT

Author: ucbjrl

build.sbt

@@ -28,15 +28,15 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
   }
 }
 
-val defaultVersions = Map("firrtl" -> "1.2.0-RC1")
+val defaultVersions = Map("firrtl" -> "1.2-091719-SNAPSHOT")
 
 lazy val commonSettings = Seq (
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),
     Resolver.sonatypeRepo("releases")
   ),
   organization := "edu.berkeley.cs",
-  version := "3.2.0-RC1",
+  version := "3.2-091719-SNAPSHOT",
   autoAPIMappings := true,
   scalaVersion := "2.12.9",
   crossScalaVersions := Seq("2.12.9", "2.11.12"),

build.sc

@@ -35,7 +35,7 @@ object chiselCompileOptions {
 val crossVersions = Seq("2.12.9", "2.11.12")
 
 // Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
-val defaultVersions = Map("firrtl" -> "1.2.0-RC1")
+val defaultVersions = Map("firrtl" -> "1.2-091719-SNAPSHOT")
 
 def getVersion(dep: String, org: String = "edu.berkeley.cs") = {
   val version = sys.env.getOrElse(dep + "Version", defaultVersions(dep))
@@ -67,7 +67,7 @@ trait CommonChiselModule extends SbtModule {
 
 trait PublishChiselModule extends CommonChiselModule with PublishModule {
   override def artifactName = "chisel3"
-  def publishVersion = "3.2.0-RC1"
+  def publishVersion = "3.2-091719-SNAPSHOT"
 
   def pomSettings = PomSettings(
     description = artifactName(),

src/main/scala/chisel3/util/Decoupled.scala

@@ -191,7 +191,8 @@ class Queue[T <: Data](gen: T,
                        flow: Boolean = false)
                       (implicit compileOptions: chisel3.CompileOptions)
     extends Module() {
-
+  require(entries > -1, "Queue must have non-negative number of entries")
+  require(entries != 0, "Use companion object Queue.apply for zero entries")
   val genType = if (compileOptions.declaredTypeMustBeUnbound) {
     requireIsChiselType(gen)
     gen
@@ -277,13 +278,12 @@ object Queue
       pipe: Boolean = false,
       flow: Boolean = false): DecoupledIO[T] = {
     if (entries == 0) {
-      val deq = Wire(new DecoupledIO(enq.bits))
+      val deq = Wire(new DecoupledIO(chiselTypeOf(enq.bits)))
       deq.valid := enq.valid
       deq.bits := enq.bits
       enq.ready := deq.ready
       deq
     } else {
-      require(entries > 0)
       val q = Module(new Queue(chiselTypeOf(enq.bits), entries, pipe, flow))
       q.io.enq.valid := enq.valid // not using <> so that override is allowed
       q.io.enq.bits := enq.bits
@@ -302,9 +302,9 @@ object Queue
       enq: ReadyValidIO[T],
       entries: Int = 2,
       pipe: Boolean = false,
-      flow: Boolean = false): IrrevocableIO[T] = {
-    require(entries > 0) // Zero-entry queues don't guarantee Irrevocability
+      flow: Boolean = false): IrrevocableIO[T] = {    
     val deq = apply(enq, entries, pipe, flow)
+    require(entries > 0, "Zero-entry queues don't guarantee Irrevocability")
     val irr = Wire(new IrrevocableIO(deq.bits))
     irr.bits := deq.bits
     irr.valid := deq.valid

src/test/scala/chiselTests/CompatibilitySpec.scala

@@ -97,6 +97,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks
       val dcd = Wire(Decoupled(data))
       dcd shouldBe a [DecoupledIO[UInt]]
       Queue(dcd) shouldBe a [DecoupledIO[UInt]]
+      Queue(dcd, 0) shouldBe a [DecoupledIO[UInt]]
       Enum(UInt(), 2) shouldBe a [List[UInt]]
       ListLookup(wire, List(wire), Array((BitPat("b1"), List(wire)))) shouldBe a [List[UInt]]
       Lookup(wire, wire, Seq((BitPat("b1"), wire))) shouldBe a [UInt]

src/test/scala/chiselTests/QueueSpec.scala

@@ -25,7 +25,7 @@ class ThingsPassThroughTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int
     inCnt.inc()
   }
   when(q.io.deq.fire()) {
-    //ensure that what comes otu is what comes in
+    //ensure that what comes out is what comes in
     assert(elems(outCnt.value) === q.io.deq.bits)
     outCnt.inc()
   }
@@ -169,6 +169,33 @@ class QueueFlowTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: I
   }
 }
 
+class QueueFactoryTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: Int) extends BasicTester {
+  val enq = Wire(Decoupled(UInt(bitWidth.W)))
+  val deq = Queue(enq, queueDepth)
+
+  val elems = VecInit(elements.map {
+    _.asUInt()
+  })
+  val inCnt = Counter(elements.length + 1)
+  val outCnt = Counter(elements.length + 1)
+
+  enq.valid := (inCnt.value < elements.length.U)
+  deq.ready := LFSR(16)(tap)
+
+  enq.bits := elems(inCnt.value)
+  when(enq.fire()) {
+    inCnt.inc()
+  }
+  when(deq.fire()) {
+    //ensure that what comes out is what comes in
+    assert(elems(outCnt.value) === deq.bits)
+    outCnt.inc()
+  }
+  when(outCnt.value === elements.length.U) {
+    stop()
+  }
+}
+
 class QueueSpec extends ChiselPropSpec {
   // Disable shrinking on error.
   implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
@@ -233,4 +260,15 @@ class QueueSpec extends ChiselPropSpec {
       }
     }
   }
+
+  property("Queue companion object factory method should work") {
+    forAll(vecSizes, safeUIntN(20), Gen.choose(0, 15)) { (depth, se, tap) =>
+      whenever(se._1 >= 1 && se._2.nonEmpty) {
+        assertTesterPasses {
+          new QueueFactoryTester(se._2, depth, se._1, tap)
+        }
+      }
+    }
+
+  }
 }