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Bump for 091719-SNAPSHOT
2 parents d442e31 + 4af6db3 commit 7e74707

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5 files changed

+49
-10
lines changed

5 files changed

+49
-10
lines changed

build.sbt

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,15 +28,15 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
2828
}
2929
}
3030

31-
val defaultVersions = Map("firrtl" -> "1.2.0-RC1")
31+
val defaultVersions = Map("firrtl" -> "1.2-091719-SNAPSHOT")
3232

3333
lazy val commonSettings = Seq (
3434
resolvers ++= Seq(
3535
Resolver.sonatypeRepo("snapshots"),
3636
Resolver.sonatypeRepo("releases")
3737
),
3838
organization := "edu.berkeley.cs",
39-
version := "3.2.0-RC1",
39+
version := "3.2-091719-SNAPSHOT",
4040
autoAPIMappings := true,
4141
scalaVersion := "2.12.9",
4242
crossScalaVersions := Seq("2.12.9", "2.11.12"),

build.sc

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ object chiselCompileOptions {
3535
val crossVersions = Seq("2.12.9", "2.11.12")
3636

3737
// Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
38-
val defaultVersions = Map("firrtl" -> "1.2.0-RC1")
38+
val defaultVersions = Map("firrtl" -> "1.2-091719-SNAPSHOT")
3939

4040
def getVersion(dep: String, org: String = "edu.berkeley.cs") = {
4141
val version = sys.env.getOrElse(dep + "Version", defaultVersions(dep))
@@ -67,7 +67,7 @@ trait CommonChiselModule extends SbtModule {
6767

6868
trait PublishChiselModule extends CommonChiselModule with PublishModule {
6969
override def artifactName = "chisel3"
70-
def publishVersion = "3.2.0-RC1"
70+
def publishVersion = "3.2-091719-SNAPSHOT"
7171

7272
def pomSettings = PomSettings(
7373
description = artifactName(),

src/main/scala/chisel3/util/Decoupled.scala

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -191,7 +191,8 @@ class Queue[T <: Data](gen: T,
191191
flow: Boolean = false)
192192
(implicit compileOptions: chisel3.CompileOptions)
193193
extends Module() {
194-
194+
require(entries > -1, "Queue must have non-negative number of entries")
195+
require(entries != 0, "Use companion object Queue.apply for zero entries")
195196
val genType = if (compileOptions.declaredTypeMustBeUnbound) {
196197
requireIsChiselType(gen)
197198
gen
@@ -277,13 +278,12 @@ object Queue
277278
pipe: Boolean = false,
278279
flow: Boolean = false): DecoupledIO[T] = {
279280
if (entries == 0) {
280-
val deq = Wire(new DecoupledIO(enq.bits))
281+
val deq = Wire(new DecoupledIO(chiselTypeOf(enq.bits)))
281282
deq.valid := enq.valid
282283
deq.bits := enq.bits
283284
enq.ready := deq.ready
284285
deq
285286
} else {
286-
require(entries > 0)
287287
val q = Module(new Queue(chiselTypeOf(enq.bits), entries, pipe, flow))
288288
q.io.enq.valid := enq.valid // not using <> so that override is allowed
289289
q.io.enq.bits := enq.bits
@@ -302,9 +302,9 @@ object Queue
302302
enq: ReadyValidIO[T],
303303
entries: Int = 2,
304304
pipe: Boolean = false,
305-
flow: Boolean = false): IrrevocableIO[T] = {
306-
require(entries > 0) // Zero-entry queues don't guarantee Irrevocability
305+
flow: Boolean = false): IrrevocableIO[T] = {
307306
val deq = apply(enq, entries, pipe, flow)
307+
require(entries > 0, "Zero-entry queues don't guarantee Irrevocability")
308308
val irr = Wire(new IrrevocableIO(deq.bits))
309309
irr.bits := deq.bits
310310
irr.valid := deq.valid

src/test/scala/chiselTests/CompatibilitySpec.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks
9797
val dcd = Wire(Decoupled(data))
9898
dcd shouldBe a [DecoupledIO[UInt]]
9999
Queue(dcd) shouldBe a [DecoupledIO[UInt]]
100+
Queue(dcd, 0) shouldBe a [DecoupledIO[UInt]]
100101
Enum(UInt(), 2) shouldBe a [List[UInt]]
101102
ListLookup(wire, List(wire), Array((BitPat("b1"), List(wire)))) shouldBe a [List[UInt]]
102103
Lookup(wire, wire, Seq((BitPat("b1"), wire))) shouldBe a [UInt]

src/test/scala/chiselTests/QueueSpec.scala

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ class ThingsPassThroughTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int
2525
inCnt.inc()
2626
}
2727
when(q.io.deq.fire()) {
28-
//ensure that what comes otu is what comes in
28+
//ensure that what comes out is what comes in
2929
assert(elems(outCnt.value) === q.io.deq.bits)
3030
outCnt.inc()
3131
}
@@ -169,6 +169,33 @@ class QueueFlowTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: I
169169
}
170170
}
171171

172+
class QueueFactoryTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: Int) extends BasicTester {
173+
val enq = Wire(Decoupled(UInt(bitWidth.W)))
174+
val deq = Queue(enq, queueDepth)
175+
176+
val elems = VecInit(elements.map {
177+
_.asUInt()
178+
})
179+
val inCnt = Counter(elements.length + 1)
180+
val outCnt = Counter(elements.length + 1)
181+
182+
enq.valid := (inCnt.value < elements.length.U)
183+
deq.ready := LFSR(16)(tap)
184+
185+
enq.bits := elems(inCnt.value)
186+
when(enq.fire()) {
187+
inCnt.inc()
188+
}
189+
when(deq.fire()) {
190+
//ensure that what comes out is what comes in
191+
assert(elems(outCnt.value) === deq.bits)
192+
outCnt.inc()
193+
}
194+
when(outCnt.value === elements.length.U) {
195+
stop()
196+
}
197+
}
198+
172199
class QueueSpec extends ChiselPropSpec {
173200
// Disable shrinking on error.
174201
implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
@@ -233,4 +260,15 @@ class QueueSpec extends ChiselPropSpec {
233260
}
234261
}
235262
}
263+
264+
property("Queue companion object factory method should work") {
265+
forAll(vecSizes, safeUIntN(20), Gen.choose(0, 15)) { (depth, se, tap) =>
266+
whenever(se._1 >= 1 && se._2.nonEmpty) {
267+
assertTesterPasses {
268+
new QueueFactoryTester(se._2, depth, se._1, tap)
269+
}
270+
}
271+
}
272+
273+
}
236274
}

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