Convert tests to circt.stage.ChiselStage (#3018)

Modify tests, other than ChiselStageSpec, to all use
circt.stage.ChiselStage and not chisel3.stage.ChiselStage.  This paves
the way for the deletion of the latter in Chisel 5.

Note: there is one bug in the Trace API resulting in a commented out
test.  This is tracked with this CIRCT issue:

  - llvm/circt#4661

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Author: seldridge

src/main/scala/chisel3/compatibility.scala

@@ -5,7 +5,9 @@
   */
 import chisel3._ // required for implicit conversions.
 import chisel3.util.random.FibonacciLFSR
-import chisel3.stage.{phases, ChiselCircuitAnnotation, ChiselOutputFileAnnotation, ChiselStage}
+import chisel3.stage.{phases, ChiselCircuitAnnotation, ChiselOutputFileAnnotation}
+
+import circt.stage.ChiselStage
 
 import scala.annotation.nowarn
 

src/test/scala/chisel3/testers/TestUtils.scala

@@ -3,9 +3,9 @@
 package chisel3.testers
 
 import chisel3.RawModule
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselPhase}
+import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.testers.TesterDriver.Backend
-import circt.stage.{CIRCTTarget, CIRCTTargetAnnotation}
+import circt.stage.{CIRCTTarget, CIRCTTargetAnnotation, ChiselStage}
 import firrtl.AnnotationSeq
 import firrtl.annotations.Annotation
 import firrtl.ir.Circuit
@@ -23,21 +23,11 @@ object TestUtils {
   // produced by it. New tests should not utilize this or getFirrtlAndAnnos
   def getChirrtlAndAnnotations(gen: => RawModule, annos: AnnotationSeq = Seq()): (Circuit, Seq[Annotation]) = {
     val dir = createTestDirectory(this.getClass.getSimpleName).toString
-    val targetDir = TargetDirAnnotation(dir)
-    val phase = new chisel3.stage.ChiselPhase {
-      override val targets = Seq(
-        Dependency[chisel3.stage.phases.Checks],
-        Dependency[chisel3.stage.phases.Elaborate],
-        Dependency[chisel3.stage.phases.AddImplicitOutputFile],
-        Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
-        Dependency[chisel3.stage.phases.MaybeAspectPhase],
-        Dependency[chisel3.stage.phases.Convert],
-        Dependency[chisel3.stage.phases.MaybeInjectingPhase]
-      )
-    }
+    val processedAnnos = (new ChiselStage).execute(
+      Array("--target-dir", dir, "--target", "chirrtl"),
+      ChiselGeneratorAnnotation(() => gen) +: annos
+    )
 
-    val processedAnnos = phase
-      .transform(Seq(ChiselGeneratorAnnotation(() => gen), targetDir) ++ annos)
     val circuit = processedAnnos.collectFirst {
       case FirrtlCircuitAnnotation(a) => a
     }.get

src/test/scala/chiselTests/AnnotatingDiamondSpec.scala

@@ -4,8 +4,9 @@ package chiselTests
 
 import chisel3._
 import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import chisel3.stage.{ChiselGeneratorAnnotation}
 import chisel3.testers.BasicTester
+import circt.stage.ChiselStage
 import firrtl.{CircuitForm, CircuitState, DependencyAPIMigration, LowForm, Transform}
 import firrtl.annotations.{CircuitName, CircuitTarget, SingleTargetAnnotation, Target}
 import firrtl.stage.Forms
@@ -143,7 +144,7 @@ class AnnotatingDiamondSpec extends AnyFreeSpec with Matchers {
 
       val annos = (new ChiselStage)
         .execute(
-          Array("--target-dir", "test_run_dir", "--no-run-firrtl"),
+          Array("--target-dir", "test_run_dir", "--target", "chirrtl"),
           Seq(ChiselGeneratorAnnotation(() => new TopOfDiamond))
         )
         .filter {

src/test/scala/chiselTests/ChiselEnum.scala

@@ -802,8 +802,8 @@ class ChiselEnumAnnotationSpec extends AnyFreeSpec with Matchers {
     corrects.forall(c => annos.exists(isCorrect(_, c)))
 
   def test(strongEnumAnnotatorGen: () => Module): Unit = {
-    val annos = (new chisel3.stage.ChiselStage).execute(
-      Array("--target-dir", "test_run_dir", "--no-run-firrtl"),
+    val annos = (new ChiselStage).execute(
+      Array("--target-dir", "test_run_dir", "--target", "chirrtl"),
       Seq(ChiselGeneratorAnnotation(strongEnumAnnotatorGen))
     )
 

src/test/scala/chiselTests/ChiselSpec.scala

@@ -5,14 +5,9 @@ package chiselTests
 import _root_.logger.Logger
 import chisel3._
 import chisel3.aop.Aspect
-import chisel3.stage.{
-  ChiselGeneratorAnnotation,
-  ChiselStage,
-  NoRunFirrtlCompilerAnnotation,
-  PrintFullStackTraceAnnotation
-}
+import chisel3.stage.{ChiselGeneratorAnnotation, NoRunFirrtlCompilerAnnotation, PrintFullStackTraceAnnotation}
 import chisel3.testers._
-import circt.stage.{CIRCTTarget, CIRCTTargetAnnotation}
+import circt.stage.{CIRCTTarget, CIRCTTargetAnnotation, ChiselStage}
 import firrtl.annotations.Annotation
 import firrtl.ir.Circuit
 import firrtl.stage.FirrtlCircuitAnnotation
@@ -93,7 +88,7 @@ trait ChiselRunners extends Assertions {
     * @return the Verilog code as a string.
     */
   def compile(t: => RawModule): String = {
-    (new circt.stage.ChiselStage)
+    (new ChiselStage)
       .execute(
         Array("--target-dir", BackendCompilationUtilities.createTestDirectory(this.getClass.getSimpleName).toString),
         Seq(ChiselGeneratorAnnotation(() => t), CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog))
@@ -303,7 +298,11 @@ trait Utils {
     // Runs chisel stage
     def run[T <: RawModule](gen: () => T, annotations: AnnotationSeq): AnnotationSeq = {
       new ChiselStage().run(
-        Seq(ChiselGeneratorAnnotation(gen), NoRunFirrtlCompilerAnnotation, PrintFullStackTraceAnnotation) ++ annotations
+        Seq(
+          ChiselGeneratorAnnotation(gen),
+          CIRCTTargetAnnotation(CIRCTTarget.CHIRRTL),
+          PrintFullStackTraceAnnotation
+        ) ++ annotations
       )
     }
     // Creates a wrapping aspect to contain checking function

src/test/scala/chiselTests/ConnectableSpec.scala

@@ -7,12 +7,12 @@ import chisel3._
 import chisel3.experimental.{Analog, FixedPoint}
 import chisel3.experimental.BundleLiterals._
 import chisel3.experimental.VecLiterals._
-import circt.stage.ChiselStage
 import chisel3.testers.BasicTester
 import chisel3.experimental.OpaqueType
 import chisel3.reflect.DataMirror
 
 import scala.annotation.nowarn
+import circt.stage.ChiselStage
 import scala.collection.immutable.SeqMap
 
 object ConnectableSpec {

src/test/scala/chiselTests/InvalidateAPISpec.scala

@@ -3,21 +3,22 @@
 package chiselTests
 
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.util.Counter
 import firrtl.passes.CheckInitialization.RefNotInitializedException
 import firrtl.util.BackendCompilationUtilities._
+import circt.stage.ChiselStage
 import org.scalatest._
 import org.scalatest.matchers.should.Matchers
 
 class InvalidateAPISpec extends ChiselPropSpec with Matchers with Utils {
 
-  def myGenerateFirrtl(t: => Module): String = ChiselStage.emitChirrtl(t)
+  def myGenerateFirrtl(t: => Module): String = ChiselStage.emitCHIRRTL(t)
   def compileFirrtl(t: => Module): Unit = {
     val testDir = createTestDirectory(this.getClass.getSimpleName)
 
     (new ChiselStage).execute(
-      Array[String]("-td", testDir.getAbsolutePath, "--compiler", "verilog"),
+      Array[String]("-td", testDir.getAbsolutePath, "--target", "verilog"),
       Seq(ChiselGeneratorAnnotation(() => t))
     )
   }

src/test/scala/chiselTests/NewAnnotationsSpec.scala

@@ -1,7 +1,8 @@
 package chiselTests
 import chisel3._
 import chisel3.experimental.{annotate, ChiselMultiAnnotation}
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import chisel3.stage.ChiselGeneratorAnnotation
+import circt.stage.ChiselStage
 import firrtl.stage.FirrtlCircuitAnnotation
 import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
@@ -51,7 +52,7 @@ class NewAnnotationsSpec extends AnyFreeSpec with Matchers {
     "NoDedup and DontTouch work as expected" in {
       val dutAnnos = stage
         .execute(
-          Array("-X", "low", "--target-dir", "test_run_dir"),
+          Array("--target", "chirrtl", "--target-dir", "test_run_dir"),
           Seq(ChiselGeneratorAnnotation(() => new UsesMuchUsedModule))
         )
 
@@ -64,8 +65,8 @@ class NewAnnotationsSpec extends AnyFreeSpec with Matchers {
 
       noDedupAnnosCombined should include("~UsesMuchUsedModule|MuchUsedModule_2")
       noDedupAnnosCombined should include("~UsesMuchUsedModule|MuchUsedModule_3")
-      dontTouchAnnosCombined should include("~UsesMuchUsedModule|UsesMuchUsedModule/mod1:MuchUsedModule>io_out")
-      dontTouchAnnosCombined should include("~UsesMuchUsedModule|UsesMuchUsedModule/mod1:MuchUsedModule>io_in")
+      dontTouchAnnosCombined should include("~UsesMuchUsedModule|MuchUsedModule_1>io.out")
+      dontTouchAnnosCombined should include("~UsesMuchUsedModule|MuchUsedModule_1>io.in")
 
     }
   }

src/test/scala/chiselTests/WarningSpec.scala

@@ -3,8 +3,8 @@
 package chiselTests
 
 import chisel3._
+import circt.stage.ChiselStage
 import chisel3.util._
-import chisel3.stage.ChiselStage
 
 class WarningSpec extends ChiselFlatSpec with Utils {
   behavior.of("Warnings")
@@ -34,7 +34,7 @@ class WarningSpec extends ChiselFlatSpec with Utils {
   "Warnings" should "be treated as errors with warningsAsErrors" in {
     a[ChiselException] should be thrownBy extractCause[ChiselException] {
       val args = Array("--warnings-as-errors")
-      (new ChiselStage).emitChirrtl(new MyModule, args)
+      ChiselStage.emitCHIRRTL(new MyModule, args)
     }
   }
 }

src/test/scala/chiselTests/experimental/SerializableModuleGeneratorSpec.scala

@@ -56,7 +56,7 @@ class SerializableModuleGeneratorSpec extends ChiselFlatSpec with Utils {
   }
 
   "SerializableModuleGenerator" should "be able to elaborate" in {
-    chisel3.stage.ChiselStage.emitChirrtl(g.module())
+    circt.stage.ChiselStage.emitCHIRRTL(g.module())
   }
 
   case class FooParameter() extends SerializableModuleParameter
@@ -66,7 +66,7 @@ class SerializableModuleGeneratorSpec extends ChiselFlatSpec with Utils {
   "InnerClass" should "not be able to serialize" in {
     assert(
       intercept[java.lang.IllegalArgumentException](
-        chisel3.stage.ChiselStage.emitChirrtl(
+        circt.stage.ChiselStage.emitCHIRRTL(
           {
             SerializableModuleGenerator(
               classOf[InnerFoo],

src/test/scala/chiselTests/experimental/TraceSpec.scala

@@ -4,8 +4,9 @@ package chiselTests
 
 import chisel3._
 import chisel3.experimental.Trace._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage, DesignAnnotation}
+import chisel3.stage.{ChiselGeneratorAnnotation, DesignAnnotation}
 import chisel3.util.experimental.InlineInstance
+import circt.stage.ChiselStage
 import firrtl.AnnotationSeq
 import firrtl.annotations.TargetToken.{Instance, OfModule, Ref}
 import firrtl.annotations.{CompleteTarget, InstanceTarget, ReferenceTarget}
@@ -24,9 +25,10 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
   def compile(testName: String, gen: () => Module): (os.Path, AnnotationSeq) = {
     val testDir = os.Path(createTestDirectory(testName).getAbsolutePath)
     val annos = (new ChiselStage).execute(
-      Array("--target-dir", s"$testDir"),
+      Array("--target-dir", s"$testDir", "--target", "systemverilog"),
       Seq(
-        ChiselGeneratorAnnotation(gen)
+        ChiselGeneratorAnnotation(gen),
+        firrtl.EmitAllModulesAnnotation(classOf[firrtl.Emitter])
       )
     )
     (testDir, annos)
@@ -161,18 +163,29 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
     }
 
     val config = os.temp(dir = testDir, contents = generateVerilatorConfigFile(Seq(dut.m0.o.a.b), annos))
-    val verilog = testDir / s"$topName.v"
+    val verilog = testDir / s"$topName.sv"
     val cpp = os.temp(dir = testDir, suffix = ".cpp", contents = verilatorTemplate(Seq(dut.m0.o.a.b), annos))
     val exe = testDir / "obj_dir" / s"V$topName"
-    os.proc("verilator", "-Wall", "--cc", "--exe", "--build", "--vpi", s"$cpp", s"$verilog", s"$config")
-      .call(stdout = os.Inherit, stderr = os.Inherit, cwd = testDir)
+    os.proc(
+      "verilator",
+      "--cc",
+      "--exe",
+      "--build",
+      "--vpi",
+      s"-I$testDir",
+      s"$cpp",
+      s"$verilog",
+      s"$config"
+    ).call(stdout = os.Inherit, stderr = os.Inherit, cwd = testDir)
     assert(
       os.proc(s"$exe").call(stdout = os.Inherit, stderr = os.Inherit).exitCode == 0,
       "verilator should exit peacefully"
     )
   }
 
-  "TraceFromCollideBundle" should "work" in {
+  // TODO: This is disabled until CIRCT 1.32 or 1.33 when there is a bug is fixed.  The CIRCT tarcking issue is:
+  //   - https://github.com/llvm/circt/issues/4661
+  "TraceFromCollideBundle" should "work" ignore {
     class CollideModule extends Module {
       val a = IO(
         Input(
@@ -224,6 +237,10 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
 
     val a0_c1_e = finalTarget(annos)(dut.a(0).c(1).e).head
     val a0_c_1_e = finalTarget(annos)(dut.a(0).c_1_e).head
+    println(dut.a(0).c(1).e.toTarget)
+    println(a0_c1_e)
+    println(dut.a(0).c_1_e.toTarget)
+    println(a0_c_1_e)
     a0_c1_e should be(refTarget(topName, "a_0_c__1_e"))
     a0_c_1_e should be(refTarget(topName, "a_0_c_1_e"))
   }
@@ -282,37 +299,37 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
 
     class M1 extends Module {
       val io = IO(new Io)
-      val not = Module(new Not)
-      not.io <> io
+      val bar = Module(new Not)
+      bar.io <> io
     }
 
     class M2 extends Module {
       val io = IO(new Io)
       val m1 = Module(new M1 with InlineInstance)
-      val not = Module(new Not)
+      val foo = Module(new Not)
 
       m1.io.i := io.i
-      not.io.i := io.i
+      foo.io.i := io.i
 
-      io.o := m1.io.o && not.io.o
+      io.o := m1.io.o && foo.io.o
     }
 
     class M3 extends Module {
       val io = IO(new Io)
       val m2 = Module(new M2)
       io <> m2.io
-      traceName(m2.not)
-      traceName(m2.m1.not)
+      traceName(m2.foo)
+      traceName(m2.m1.bar)
     }
 
     val (_, annos) = compile("NestedModule", () => new M3)
     val m3 = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[M3]
 
-    val m2_m1_not = finalTarget(annos)(m3.m2.m1.not).head
-    val m2_not = finalTarget(annos)(m3.m2.not).head
+    val m2_m1_not = finalTarget(annos)(m3.m2.m1.bar).head
+    val m2_not = finalTarget(annos)(m3.m2.foo).head
 
-    m2_m1_not should be(instTarget("M3", "m1_not", "Not", Seq(Instance("m2") -> OfModule("M2"))))
-    m2_not should be(instTarget("M3", "not", "Not", Seq(Instance("m2") -> OfModule("M2"))))
+    m2_m1_not should be(instTarget("M3", "bar", "Not", Seq(Instance("m2") -> OfModule("M2"))))
+    m2_not should be(instTarget("M3", "foo", "Not", Seq(Instance("m2") -> OfModule("M2"))))
   }
 
   "All traced signal" should "generate" in {