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Merge branch 'master' into release
# Conflicts: # build.sbt
2 parents fb9644d + 666512f commit 86c0f76

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6 files changed

+33
-18
lines changed

6 files changed

+33
-18
lines changed

build.sbt

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@ lazy val commonSettings = Seq (
1717
organization := "edu.berkeley.cs",
1818
version := "3.0-SNAPSHOT_2017-05-25",
1919
git.remoteRepo := "git@github.com:ucb-bar/chisel3.git",
20-
scalaVersion := "2.11.7",
2120
autoAPIMappings := true,
21+
scalaVersion := "2.11.11",
2222
resolvers ++= Seq(
2323
Resolver.sonatypeRepo("snapshots"),
2424
Resolver.sonatypeRepo("releases")
@@ -86,9 +86,9 @@ lazy val chiselSettings = Seq (
8686
dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }),
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8888
libraryDependencies ++= Seq(
89-
"org.scalatest" %% "scalatest" % "2.2.5" % "test",
90-
"org.scalacheck" %% "scalacheck" % "1.12.4" % "test",
91-
"com.github.scopt" %% "scopt" % "3.4.0"
89+
"org.scalatest" %% "scalatest" % "3.0.1" % "test",
90+
"org.scalacheck" %% "scalacheck" % "1.13.4" % "test",
91+
"com.github.scopt" %% "scopt" % "3.5.0"
9292
),
9393

9494
// Tests from other projects may still run concurrently.

project/build.properties

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
sbt.version=0.13.12
1+
sbt.version=0.13.15

project/plugins.sbt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ addSbtPlugin("com.typesafe.sbt" % "sbt-pgp" % "0.8.3")
88

99
addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "0.8.0")
1010

11-
addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.3.5")
11+
addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.0")
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1313
addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.5.4")
1414

src/main/scala/chisel3/util/Decoupled.scala

Lines changed: 24 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -10,9 +10,11 @@ import chisel3.internal.naming._ // can't use chisel3_ version because of compi
1010

1111
/** An I/O Bundle containing 'valid' and 'ready' signals that handshake
1212
* the transfer of data stored in the 'bits' subfield.
13-
* The base protocol implied by the directionality is that the consumer
14-
* uses the flipped interface. Actual semantics of ready/valid are
15-
* enforced via use of concrete subclasses.
13+
* The base protocol implied by the directionality is that
14+
* the producer uses the interface as-is (outputs bits)
15+
* while the consumer uses the flipped interface (inputs bits).
16+
* The actual semantics of ready/valid are enforced via the use of concrete subclasses.
17+
* @param gen the type of data to be wrapped in Ready/Valid
1618
*/
1719
abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle
1820
{
@@ -47,7 +49,6 @@ object ReadyValidIO {
4749

4850
/** Assert ready on this port and return the associated data bits.
4951
* This is typically used when valid has been asserted by the producer side.
50-
* @param b ignored
5152
* @return the data for this device,
5253
*/
5354
def deq(): T = {
@@ -68,6 +69,7 @@ object ReadyValidIO {
6869
* put valid data in 'bits', and 'ready' indicates that the consumer is ready
6970
* to accept the data this cycle. No requirements are placed on the signaling
7071
* of ready or valid.
72+
* @param gen the type of data to be wrapped in DecoupledIO
7173
*/
7274
class DecoupledIO[+T <: Data](gen: T) extends ReadyValidIO[T](gen)
7375
{
@@ -102,6 +104,7 @@ object Decoupled
102104
* the value of 'bits' after a cycle where 'valid' is high and 'ready' is low.
103105
* Additionally, once 'valid' is raised it will never be lowered until after
104106
* 'ready' has also been raised.
107+
* @param gen the type of data to be wrapped in IrrevocableIO
105108
*/
106109
class IrrevocableIO[+T <: Data](gen: T) extends ReadyValidIO[T](gen)
107110
{
@@ -128,22 +131,33 @@ object Irrevocable
128131
}
129132
}
130133

134+
/** Producer - drives (outputs) valid and bits, inputs ready.
135+
* @param gen The type of data to enqueue
136+
*/
131137
object EnqIO {
132138
def apply[T<:Data](gen: T): DecoupledIO[T] = Decoupled(gen)
133139
}
140+
/** Consumer - drives (outputs) ready, inputs valid and bits.
141+
* @param gen The type of data to dequeue
142+
*/
134143
object DeqIO {
135144
def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(Decoupled(gen))
136145
}
137146

138147
/** An I/O Bundle for Queues
139148
* @param gen The type of data to queue
140-
* @param entries The max number of entries in the queue */
149+
* @param entries The max number of entries in the queue.
150+
*/
141151
class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
142152
{
143-
/** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */
144-
val enq = DeqIO(gen)
145-
/** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
146-
val deq = EnqIO(gen)
153+
/* These may look inverted, because the names (enq/deq) are from the perspective of the client,
154+
* but internally, the queue implementation itself sits on the other side
155+
* of the interface so uses the flipped instance.
156+
*/
157+
/** I/O to enqueue data (client is producer, and Queue object is consumer), is [[Chisel.DecoupledIO]] flipped. */
158+
val enq = Flipped(EnqIO(gen))
159+
/** I/O to dequeue data (client is consumer and Queue object is producer), is [[Chisel.DecoupledIO]]*/
160+
val deq = Flipped(DeqIO(gen))
147161
/** The current amount of data in the queue */
148162
val count = Output(UInt(log2Ceil(entries + 1).W))
149163

@@ -159,7 +173,7 @@ class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
159173
* The ''valid'' signals are coupled.
160174
*
161175
* @example {{{
162-
* val q = new Queue(UInt(), 16)
176+
* val q = Module(new Queue(UInt(), 16))
163177
* q.io.enq <> producer.io.out
164178
* consumer.io.in <> q.io.deq
165179
* }}}

src/test/scala/chiselTests/ChiselSpec.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ class ChiselPropSpec extends PropSpec with ChiselRunners with PropertyChecks wit
6868

6969
// Constrain the default number of instances generated for every use of forAll.
7070
implicit override val generatorDrivenConfig =
71-
PropertyCheckConfig(minSuccessful = 8, minSize = 1, maxSize = 4)
71+
PropertyCheckConfiguration(minSuccessful = 8, minSize = 1, sizeRange = 3)
7272

7373
// Generator for small positive integers.
7474
val smallPosInts = Gen.choose(1, 4)

src/test/scala/chiselTests/Direction.scala

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@ package chiselTests
44

55
import chisel3._
66
import org.scalatest._
7+
import org.scalatest.matchers._
78
import org.scalatest.prop._
89
import chisel3.testers.BasicTester
910

@@ -22,7 +23,7 @@ class BadDirection extends DirectionHaver {
2223
io.in := 0.U
2324
}
2425

25-
class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
26+
class DirectionSpec extends ChiselPropSpec with Matchers {
2627

2728
//TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests?
2829

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