@@ -10,9 +10,11 @@ import chisel3.internal.naming._ // can't use chisel3_ version because of compi
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/** An I/O Bundle containing 'valid' and 'ready' signals that handshake
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* the transfer of data stored in the 'bits' subfield.
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- * The base protocol implied by the directionality is that the consumer
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- * uses the flipped interface. Actual semantics of ready/valid are
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- * enforced via use of concrete subclasses.
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+ * The base protocol implied by the directionality is that
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+ * the producer uses the interface as-is (outputs bits)
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+ * while the consumer uses the flipped interface (inputs bits).
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+ * The actual semantics of ready/valid are enforced via the use of concrete subclasses.
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+ * @param gen the type of data to be wrapped in Ready/Valid
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*/
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abstract class ReadyValidIO [+ T <: Data ](gen : T ) extends Bundle
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{
@@ -47,7 +49,6 @@ object ReadyValidIO {
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/** Assert ready on this port and return the associated data bits.
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* This is typically used when valid has been asserted by the producer side.
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- * @param b ignored
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* @return the data for this device,
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*/
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def deq (): T = {
@@ -68,6 +69,7 @@ object ReadyValidIO {
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* put valid data in 'bits', and 'ready' indicates that the consumer is ready
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* to accept the data this cycle. No requirements are placed on the signaling
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* of ready or valid.
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+ * @param gen the type of data to be wrapped in DecoupledIO
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*/
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class DecoupledIO [+ T <: Data ](gen : T ) extends ReadyValidIO [T ](gen)
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{
@@ -102,6 +104,7 @@ object Decoupled
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* the value of 'bits' after a cycle where 'valid' is high and 'ready' is low.
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* Additionally, once 'valid' is raised it will never be lowered until after
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* 'ready' has also been raised.
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+ * @param gen the type of data to be wrapped in IrrevocableIO
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*/
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class IrrevocableIO [+ T <: Data ](gen : T ) extends ReadyValidIO [T ](gen)
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{
@@ -128,22 +131,33 @@ object Irrevocable
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}
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}
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+ /** Producer - drives (outputs) valid and bits, inputs ready.
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+ * @param gen The type of data to enqueue
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+ */
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object EnqIO {
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def apply [T <: Data ](gen : T ): DecoupledIO [T ] = Decoupled (gen)
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}
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+ /** Consumer - drives (outputs) ready, inputs valid and bits.
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+ * @param gen The type of data to dequeue
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+ */
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object DeqIO {
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def apply [T <: Data ](gen : T ): DecoupledIO [T ] = Flipped (Decoupled (gen))
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}
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/** An I/O Bundle for Queues
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* @param gen The type of data to queue
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- * @param entries The max number of entries in the queue */
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+ * @param entries The max number of entries in the queue.
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+ */
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class QueueIO [T <: Data ](gen : T , entries : Int ) extends Bundle
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{
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- /** I/O to enqueue data, is [[Chisel.DecoupledIO ]] flipped */
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- val enq = DeqIO (gen)
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- /** I/O to enqueue data, is [[Chisel.DecoupledIO ]]*/
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- val deq = EnqIO (gen)
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+ /* These may look inverted, because the names (enq/deq) are from the perspective of the client,
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+ * but internally, the queue implementation itself sits on the other side
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+ * of the interface so uses the flipped instance.
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+ */
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+ /** I/O to enqueue data (client is producer, and Queue object is consumer), is [[Chisel.DecoupledIO ]] flipped. */
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+ val enq = Flipped (EnqIO (gen))
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+ /** I/O to dequeue data (client is consumer and Queue object is producer), is [[Chisel.DecoupledIO ]]*/
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+ val deq = Flipped (DeqIO (gen))
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/** The current amount of data in the queue */
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val count = Output (UInt (log2Ceil(entries + 1 ).W ))
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@@ -159,7 +173,7 @@ class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
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* The ''valid'' signals are coupled.
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*
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* @example {{{
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- * val q = new Queue(UInt(), 16)
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+ * val q = Module( new Queue(UInt(), 16) )
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* q.io.enq <> producer.io.out
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* consumer.io.in <> q.io.deq
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* }}}
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