Revert "Literals set their ref so they no longer get named (#826)"

This reverts commit d0cdd3b.

chiselFrontend/src/main/scala/chisel3/core/Bits.scala

@@ -67,9 +67,6 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
   // Arguments for: self-checking code (can't do arithmetic on bits)
   // Arguments against: generates down to a FIRRTL UInt anyways
 
-  // If this is a literal, setRef so that we don't allocate a name
-  litArg.foreach(setRef)
-
   // Only used for in a few cases, hopefully to be removed
   private[core] def cloneTypeWidth(width: Width): this.type
 

src/test/scala/chiselTests/DedupSpec.scala

@@ -41,31 +41,6 @@ class NestedDedup extends Module {
   io.out <> inst1.io.out
 }
 
-object DedupConsts {
-  val foo = 3.U
-}
-
-class SharedConstantValDedup extends Module {
-  val io = IO(new Bundle {
-    val in = Input(UInt(8.W))
-    val out = Output(UInt(8.W))
-  })
-  io.out := io.in + DedupConsts.foo
-}
-
-class SharedConstantValDedupTop extends Module {
-  val io = IO(new Bundle {
-    val in = Input(UInt(8.W))
-    val out = Output(UInt(8.W))
-  })
-  val inst0 = Module(new SharedConstantValDedup)
-  val inst1 = Module(new SharedConstantValDedup)
-  inst0.io.in := io.in
-  inst1.io.in := io.in
-  io.out := inst0.io.out + inst1.io.out
-}
-
-
 class DedupSpec extends ChiselFlatSpec {
   private val ModuleRegex = """\s*module\s+(\w+)\b.*""".r
   def countModules(verilog: String): Int =
@@ -78,9 +53,5 @@ class DedupSpec extends ChiselFlatSpec {
   it should "properly dedup modules with deduped submodules" in {
     assert(countModules(compile { new NestedDedup }) === 3)
   }
-
-  it should "dedup modules that share a literal" in {
-    assert(countModules(compile { new SharedConstantValDedupTop  }) === 2)
-  }
 }
 

src/test/scala/chiselTests/MultiClockSpec.scala

@@ -142,18 +142,6 @@ class MultiClockSpec extends ChiselFlatSpec {
       assert(withReset(this.reset) { 5 } == 5)
     })
   }
-  it should "support literal Bools" in {
-    assertTesterPasses(new BasicTester {
-      val reg = withReset(true.B) {
-        RegInit(6.U)
-      }
-      reg := reg - 1.U
-      // The reg is always in reset so will never decrement
-      chisel3.assert(reg === 6.U)
-      val (_, done) = Counter(true.B, 4)
-      when (done) { stop() }
-    })
-  }
 
   "withClockAndReset" should "return like a normal Scala block" in {
     elaborate(new BasicTester {