Scope resources - move them down into chisel3 directory - fixes #549 (#610)

Author: ucbjrl

src/main/resources/Makefile renamed to src/main/resources/chisel3/Makefile

@@ -28,7 +28,7 @@ object TesterDriver extends BackendCompilationUtilities {
 
     // Copy CPP harness and other Verilog sources from resources into files
     val cppHarness =  new File(path, "top.cpp")
-    copyResourceToFile("/top.cpp", cppHarness)
+    copyResourceToFile("/chisel3/top.cpp", cppHarness)
     val additionalVFiles = additionalVResources.map((name: String) => {
       val mangledResourceName = name.replace("/", "_")
       val out = new File(path, mangledResourceName)

src/main/resources/top.cpp renamed to src/main/resources/chisel3/top.cpp

@@ -126,10 +126,10 @@ class AnalogIntegrationTester(mod: => AnalogDUTModule) extends BasicTester {
 class AnalogIntegrationSpec extends ChiselFlatSpec {
   behavior of "Verilator"
   it should "support simple bidirectional wires" in {
-    assertTesterPasses(new AnalogIntegrationTester(new AnalogSmallDUT), Seq("/AnalogBlackBox.v"))
+    assertTesterPasses(new AnalogIntegrationTester(new AnalogSmallDUT), Seq("/chisel3/AnalogBlackBox.v"))
   }
   // Use this test once Verilator supports alias
   ignore should "support arbitrary bidirectional wires" in {
-    assertTesterPasses(new AnalogIntegrationTester(new AnalogDUT), Seq("/AnalogBlackBox.v"))
+    assertTesterPasses(new AnalogIntegrationTester(new AnalogDUT), Seq("/chisel3/AnalogBlackBox.v"))
   }
 }

src/main/scala/chisel3/testers/TesterDriver.scala

@@ -130,7 +130,7 @@ class AnalogSpec extends ChiselFlatSpec {
       val mod = Module(new AnalogReaderBlackBox)
       mod.io.bus <> writer.io.bus
       check(mod)
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "error if any bulk connected more than once" in {
@@ -149,7 +149,7 @@ class AnalogSpec extends ChiselFlatSpec {
       val mods = Seq.fill(2)(Module(new AnalogReaderBlackBox))
       attach(writer.io.bus, mods(0).io.bus, mods(1).io.bus)
       mods.foreach(check(_))
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "work with 3 blackboxes separately attached via a wire" in {
@@ -160,7 +160,7 @@ class AnalogSpec extends ChiselFlatSpec {
       attach(busWire, mods(0).io.bus)
       attach(mods(1).io.bus, busWire)
       mods.foreach(check(_))
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   // This does not currently work in Verilator unless Firrtl does constant prop and dead code
@@ -173,7 +173,7 @@ class AnalogSpec extends ChiselFlatSpec {
       attach(busWire(1), mod.io.bus)
       attach(busWire(0), busWire(1))
       check(mod)
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "work with blackboxes at different levels of the module hierarchy" in {
@@ -182,7 +182,7 @@ class AnalogSpec extends ChiselFlatSpec {
       val busWire = Wire(writer.io.bus)
       attach(writer.io.bus, mods(0).io.bus, mods(1).io.bus)
       mods.foreach(check(_))
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   // This does not currently work in Verilator, but does work in VCS
@@ -193,7 +193,7 @@ class AnalogSpec extends ChiselFlatSpec {
       connector.io.bus1 <> writer.io.bus
       reader.io.bus <> connector.io.bus2
       check(reader)
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "NOT support conditional connection of analog types" in {
@@ -204,7 +204,7 @@ class AnalogSpec extends ChiselFlatSpec {
           mod.io.bus <> writer.io.bus
         }
         check(mod)
-      }, Seq("/AnalogBlackBox.v"))
+      }, Seq("/chisel3/AnalogBlackBox.v"))
     }
   }
 }

src/test/resources/AnalogBlackBox.v renamed to src/test/resources/chisel3/AnalogBlackBox.v

@@ -138,18 +138,18 @@ class BlackBoxWithParamsTester extends BasicTester {
 class BlackBoxSpec extends ChiselFlatSpec {
   "A BlackBoxed inverter" should "work" in {
     assertTesterPasses({ new BlackBoxTester },
-        Seq("/BlackBoxTest.v"))
+        Seq("/chisel3/BlackBoxTest.v"))
   }
   "Multiple BlackBoxes" should "work" in {
     assertTesterPasses({ new MultiBlackBoxTester },
-        Seq("/BlackBoxTest.v"))
+        Seq("/chisel3/BlackBoxTest.v"))
   }
   "A BlackBoxed register" should "work" in {
     assertTesterPasses({ new BlackBoxWithClockTester },
-        Seq("/BlackBoxTest.v"))
+        Seq("/chisel3/BlackBoxTest.v"))
   }
   "BlackBoxes with parameters" should "work" in {
     assertTesterPasses({ new BlackBoxWithParamsTester },
-        Seq("/BlackBoxTest.v"))
+        Seq("/chisel3/BlackBoxTest.v"))
   }
 }

src/test/resources/BlackBoxTest.v renamed to src/test/resources/chisel3/BlackBoxTest.v

@@ -47,7 +47,7 @@ class BlackBoxMinus extends HasBlackBoxResource {
     val in2 = Input(UInt(16.W))
     val out = Output(UInt(16.W))
   })
-  setResource("/BlackBoxTest.v")
+  setResource("/chisel3/BlackBoxTest.v")
 }
 
 class UsesBlackBoxMinusViaResource extends Module {

src/test/resources/VerilogVendingMachine.v renamed to src/test/resources/chisel3/VerilogVendingMachine.v

@@ -62,10 +62,10 @@ class MultiExtModuleTester extends BasicTester {
 class ExtModuleSpec extends ChiselFlatSpec {
   "A ExtModule inverter" should "work" in {
     assertTesterPasses({ new ExtModuleTester },
-        Seq("/BlackBoxTest.v"))
+        Seq("/chisel3/BlackBoxTest.v"))
   }
   "Multiple ExtModules" should "work" in {
     assertTesterPasses({ new MultiExtModuleTester },
-        Seq("/BlackBoxTest.v"))
+        Seq("/chisel3/BlackBoxTest.v"))
   }
 }

src/test/scala/chiselTests/AnalogIntegrationSpec.scala

@@ -90,6 +90,6 @@ class SimpleVendingMachineSpec extends ChiselFlatSpec {
   }
   "An Verilog implementation of a vending machine" should "work" in {
     assertTesterPasses(new SimpleVendingMachineTester(new VerilogVendingMachineWrapper),
-                       List("/VerilogVendingMachine.v"))
+                       List("/chisel3/VerilogVendingMachine.v"))
   }
 }