@@ -33,23 +33,23 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers {
33
33
}
34
34
35
35
class BoundDataModule extends MultiIOModule { // not in the test to avoid anon naming suffixes
36
- Wire (UInt ()).toString should be(" UInt(Wire in DataPrintSpec$ BoundDataModule)" )
37
- Reg (SInt ()).toString should be(" SInt(Reg in DataPrintSpec$ BoundDataModule)" )
36
+ Wire (UInt ()).toString should be(" UInt(Wire in BoundDataModule)" )
37
+ Reg (SInt ()).toString should be(" SInt(Reg in BoundDataModule)" )
38
38
val io = IO (Output (Bool ())) // needs a name so elaboration doesn't fail
39
- io.toString should be(" Bool(IO in unelaborated DataPrintSpec$ BoundDataModule)" )
39
+ io.toString should be(" Bool(IO in unelaborated BoundDataModule)" )
40
40
val m = Mem (4 , UInt (2 .W ))
41
- m(2 ).toString should be(" UInt<2>(MemPort in DataPrintSpec$ BoundDataModule)" )
42
- (2 .U + 2 .U ).toString should be(" UInt<2>(OpResult in DataPrintSpec$ BoundDataModule)" )
43
- Wire (Vec (3 , UInt (2 .W ))).toString should be (" UInt<2>[3](Wire in DataPrintSpec$ BoundDataModule)" )
41
+ m(2 ).toString should be(" UInt<2>(MemPort in BoundDataModule)" )
42
+ (2 .U + 2 .U ).toString should be(" UInt<2>(OpResult in BoundDataModule)" )
43
+ Wire (Vec (3 , UInt (2 .W ))).toString should be (" UInt<2>[3](Wire in BoundDataModule)" )
44
44
45
45
class InnerModule extends MultiIOModule {
46
46
val io = IO (Output (new Bundle {
47
47
val a = UInt (4 .W )
48
48
}))
49
49
}
50
50
val inner = Module (new InnerModule )
51
- inner.clock.toString should be (" Clock(IO clock in DataPrintSpec$BoundDataModule$ InnerModule)" )
52
- inner.io.a.toString should be (" UInt<4>(IO io_a in DataPrintSpec$BoundDataModule$ InnerModule)" )
51
+ inner.clock.toString should be (" Clock(IO clock in InnerModule)" )
52
+ inner.io.a.toString should be (" UInt<4>(IO io_a in InnerModule)" )
53
53
}
54
54
55
55
" Bound data types" should " have a meaningful string representation" in {
0 commit comments