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Added API to get Verilog from Chisel (#676)
* Added API to get Verilog from Chisel * Removed second emitVerilog implementation, added scaladoc
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src/main/scala/chisel3/Driver.scala

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@@ -95,6 +95,18 @@ object Driver extends BackendCompilationUtilities {
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def emit[T <: RawModule](ir: Circuit): String = Emitter.emit(ir)
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/** Elaborates the Module specified in the gen function into Verilog
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*
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* @param gen a function that creates a Module hierarchy
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* @return the resulting String containing the design in Verilog
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*/
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def emitVerilog[T <: RawModule](gen: => T): String = {
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execute(Array[String](), { () => gen }) match {
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case ChiselExecutionSuccess(_, _, Some(firrtl.FirrtlExecutionSuccess(_, verilog))) => verilog
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case _ => sys.error("Cannot get Verilog!")
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}
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}
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def dumpFirrtl(ir: Circuit, optName: Option[File]): File = {
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val f = optName.getOrElse(new File(ir.name + ".fir"))
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val w = new FileWriter(f)

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