Bump for 3.2.0 release

Author: ucbjrl

build.sbt

@@ -28,15 +28,15 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
   }
 }
 
-val defaultVersions = Map("firrtl" -> "1.2-100219-SNAPSHOT")
+val defaultVersions = Map("firrtl" -> "1.2.0")
 
 lazy val commonSettings = Seq (
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),
     Resolver.sonatypeRepo("releases")
   ),
   organization := "edu.berkeley.cs",
-  version := "3.2-100219-SNAPSHOT",
+  version := "3.2.0",
   autoAPIMappings := true,
   scalaVersion := "2.12.10",
   crossScalaVersions := Seq("2.12.10", "2.11.12"),

build.sc

@@ -35,7 +35,7 @@ object chiselCompileOptions {
 val crossVersions = Seq("2.12.10", "2.11.12")
 
 // Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
-val defaultVersions = Map("firrtl" -> "1.2-100219-SNAPSHOT")
+val defaultVersions = Map("firrtl" -> "1.2.0")
 
 def getVersion(dep: String, org: String = "edu.berkeley.cs") = {
   val version = sys.env.getOrElse(dep + "Version", defaultVersions(dep))
@@ -67,7 +67,7 @@ trait CommonChiselModule extends SbtModule {
 
 trait PublishChiselModule extends CommonChiselModule with PublishModule {
   override def artifactName = "chisel3"
-  def publishVersion = "3.2-100219-SNAPSHOT"
+  def publishVersion = "3.2.0"
 
   def pomSettings = PomSettings(
     description = artifactName(),

chiselFrontend/src/main/scala/chisel3/Aggregate.scala

@@ -156,7 +156,9 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int)
       child.bind(ChildBinding(this), resolvedDirection)
     }
 
-    direction = sample_element.direction
+    // Since all children are the same, we can just use the sample_element rather than all children
+    // .get is safe because None means mixed directions, we only pass 1 so that's not possible
+    direction = ActualDirection.fromChildren(Set(sample_element.direction), resolvedDirection).get
   }
 
   // Note: the constructor takes a gen() function instead of a Seq to enforce

chiselFrontend/src/main/scala/chisel3/Module.scala

@@ -221,7 +221,7 @@ package experimental {
     /** Desired name of this module. Override this to give this module a custom, perhaps parametric,
       * name.
       */
-    def desiredName: String = this.getClass.getName.split('.').last
+    def desiredName: String = this.getClass.getName.split("\\.|\\$").last
 
     /** Legalized name of this module. */
     final lazy val name = try {

src/test/scala/chiselTests/DataPrint.scala

@@ -33,23 +33,23 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers {
   }
 
   class BoundDataModule extends MultiIOModule {  // not in the test to avoid anon naming suffixes
-    Wire(UInt()).toString should be("UInt(Wire in DataPrintSpec$BoundDataModule)")
-    Reg(SInt()).toString should be("SInt(Reg in DataPrintSpec$BoundDataModule)")
+    Wire(UInt()).toString should be("UInt(Wire in BoundDataModule)")
+    Reg(SInt()).toString should be("SInt(Reg in BoundDataModule)")
     val io = IO(Output(Bool()))  // needs a name so elaboration doesn't fail
-    io.toString should be("Bool(IO in unelaborated DataPrintSpec$BoundDataModule)")
+    io.toString should be("Bool(IO in unelaborated BoundDataModule)")
     val m = Mem(4, UInt(2.W))
-    m(2).toString should be("UInt<2>(MemPort in DataPrintSpec$BoundDataModule)")
-    (2.U + 2.U).toString should be("UInt<2>(OpResult in DataPrintSpec$BoundDataModule)")
-    Wire(Vec(3, UInt(2.W))).toString should be ("UInt<2>[3](Wire in DataPrintSpec$BoundDataModule)")
+    m(2).toString should be("UInt<2>(MemPort in BoundDataModule)")
+    (2.U + 2.U).toString should be("UInt<2>(OpResult in BoundDataModule)")
+    Wire(Vec(3, UInt(2.W))).toString should be ("UInt<2>[3](Wire in BoundDataModule)")
 
     class InnerModule extends MultiIOModule {
       val io = IO(Output(new Bundle {
         val a = UInt(4.W)
       }))
     }
     val inner = Module(new InnerModule)
-    inner.clock.toString should be ("Clock(IO clock in DataPrintSpec$BoundDataModule$InnerModule)")
-    inner.io.a.toString should be ("UInt<4>(IO io_a in DataPrintSpec$BoundDataModule$InnerModule)")
+    inner.clock.toString should be ("Clock(IO clock in InnerModule)")
+    inner.io.a.toString should be ("UInt<4>(IO io_a in InnerModule)")
   }
 
   "Bound data types" should "have a meaningful string representation" in {

src/test/scala/chiselTests/Direction.scala

@@ -205,27 +205,37 @@ class DirectionSpec extends ChiselPropSpec with Matchers {
         val b = Output(Bool())
       }
 
+      val index = IO(Input(UInt(1.W)))
+
       // Check all permutations of Vec and Flipped.
-      val regularVec = IO(Vec(1, new MyBundle))
+      val regularVec = IO(Vec(2, new MyBundle))
       regularVec <> DontCare
       assert(DataMirror.directionOf(regularVec.head.a) == Direction.Input)
       assert(DataMirror.directionOf(regularVec.head.b) == Direction.Output)
+      assert(DataMirror.directionOf(regularVec(index).a) == Direction.Input)
+      assert(DataMirror.directionOf(regularVec(index).b) == Direction.Output)
 
-      val vecFlipped = IO(Vec(1, Flipped(new MyBundle)))
+      val vecFlipped = IO(Vec(2, Flipped(new MyBundle)))
       vecFlipped <> DontCare
       assert(DataMirror.directionOf(vecFlipped.head.a) == Direction.Output)
       assert(DataMirror.directionOf(vecFlipped.head.b) == Direction.Input)
+      assert(DataMirror.directionOf(vecFlipped(index).a) == Direction.Output)
+      assert(DataMirror.directionOf(vecFlipped(index).b) == Direction.Input)
 
-      val flippedVec = IO(Flipped(Vec(1, new MyBundle)))
+      val flippedVec = IO(Flipped(Vec(2, new MyBundle)))
       flippedVec <> DontCare
       assert(DataMirror.directionOf(flippedVec.head.a) == Direction.Output)
       assert(DataMirror.directionOf(flippedVec.head.b) == Direction.Input)
+      assert(DataMirror.directionOf(flippedVec(index).a) == Direction.Output)
+      assert(DataMirror.directionOf(flippedVec(index).b) == Direction.Input)
 
       // Flipped(Vec(Flipped())) should be equal to non-flipped.
-      val flippedVecFlipped = IO(Flipped(Vec(1, Flipped(new MyBundle))))
+      val flippedVecFlipped = IO(Flipped(Vec(2, Flipped(new MyBundle))))
       flippedVecFlipped <> DontCare
       assert(DataMirror.directionOf(flippedVecFlipped.head.a) == Direction.Input)
       assert(DataMirror.directionOf(flippedVecFlipped.head.b) == Direction.Output)
+      assert(DataMirror.directionOf(flippedVecFlipped(index).a) == Direction.Input)
+      assert(DataMirror.directionOf(flippedVecFlipped(index).b) == Direction.Output)
     }
 
     val elaborated = Driver.elaborate(() => new MyModule)
@@ -238,10 +248,10 @@ class DirectionSpec extends ChiselPropSpec with Matchers {
       // Chisel Emitter formats spacing a little differently than the
       // FIRRTL Emitter :-(
       val s = o.replace("{flip a", "{ flip a")
-      assert(s.contains("output regularVec : { flip a : UInt<1>, b : UInt<1>}[1]"))
-      assert(s.contains("input vecFlipped : { flip a : UInt<1>, b : UInt<1>}[1]"))
-      assert(s.contains("input flippedVec : { flip a : UInt<1>, b : UInt<1>}[1]"))
-      assert(s.contains("output flippedVecFlipped : { flip a : UInt<1>, b : UInt<1>}[1]"))
+      assert(s.contains("output regularVec : { flip a : UInt<1>, b : UInt<1>}[2]"))
+      assert(s.contains("input vecFlipped : { flip a : UInt<1>, b : UInt<1>}[2]"))
+      assert(s.contains("input flippedVec : { flip a : UInt<1>, b : UInt<1>}[2]"))
+      assert(s.contains("output flippedVecFlipped : { flip a : UInt<1>, b : UInt<1>}[2]"))
     } }
   }
 
@@ -252,35 +262,49 @@ class DirectionSpec extends ChiselPropSpec with Matchers {
         val b = Output(Bool())
       }
 
-      val inputVec = IO(Vec(1, Input(new MyBundle)))
+      val index = IO(Input(UInt(1.W)))
+
+      val inputVec = IO(Vec(2, Input(new MyBundle)))
       inputVec <> DontCare
       assert(DataMirror.directionOf(inputVec.head.a) == Direction.Input)
       assert(DataMirror.directionOf(inputVec.head.b) == Direction.Input)
+      assert(DataMirror.directionOf(inputVec(index).a) == Direction.Input)
+      assert(DataMirror.directionOf(inputVec(index).b) == Direction.Input)
 
-      val vecInput = IO(Input(Vec(1, new MyBundle)))
+      val vecInput = IO(Input(Vec(2, new MyBundle)))
       vecInput <> DontCare
       assert(DataMirror.directionOf(vecInput.head.a) == Direction.Input)
       assert(DataMirror.directionOf(vecInput.head.b) == Direction.Input)
+      assert(DataMirror.directionOf(vecInput(index).a) == Direction.Input)
+      assert(DataMirror.directionOf(vecInput(index).b) == Direction.Input)
 
-      val vecInputFlipped = IO(Input(Vec(1, Flipped(new MyBundle))))
+      val vecInputFlipped = IO(Input(Vec(2, Flipped(new MyBundle))))
       vecInputFlipped <> DontCare
       assert(DataMirror.directionOf(vecInputFlipped.head.a) == Direction.Input)
       assert(DataMirror.directionOf(vecInputFlipped.head.b) == Direction.Input)
+      assert(DataMirror.directionOf(vecInputFlipped(index).a) == Direction.Input)
+      assert(DataMirror.directionOf(vecInputFlipped(index).b) == Direction.Input)
 
-      val outputVec = IO(Vec(1, Output(new MyBundle)))
+      val outputVec = IO(Vec(2, Output(new MyBundle)))
       outputVec <> DontCare
       assert(DataMirror.directionOf(outputVec.head.a) == Direction.Output)
       assert(DataMirror.directionOf(outputVec.head.b) == Direction.Output)
+      assert(DataMirror.directionOf(outputVec(index).a) == Direction.Output)
+      assert(DataMirror.directionOf(outputVec(index).b) == Direction.Output)
 
-      val vecOutput = IO(Output(Vec(1, new MyBundle)))
+      val vecOutput = IO(Output(Vec(2, new MyBundle)))
       vecOutput <> DontCare
       assert(DataMirror.directionOf(vecOutput.head.a) == Direction.Output)
       assert(DataMirror.directionOf(vecOutput.head.b) == Direction.Output)
+      assert(DataMirror.directionOf(vecOutput(index).a) == Direction.Output)
+      assert(DataMirror.directionOf(vecOutput(index).b) == Direction.Output)
 
-      val vecOutputFlipped = IO(Output(Vec(1, Flipped(new MyBundle))))
+      val vecOutputFlipped = IO(Output(Vec(2, Flipped(new MyBundle))))
       vecOutputFlipped <> DontCare
       assert(DataMirror.directionOf(vecOutputFlipped.head.a) == Direction.Output)
       assert(DataMirror.directionOf(vecOutputFlipped.head.b) == Direction.Output)
+      assert(DataMirror.directionOf(vecOutputFlipped(index).a) == Direction.Output)
+      assert(DataMirror.directionOf(vecOutputFlipped(index).b) == Direction.Output)
     }
 
     val elaborated = Driver.elaborate(() => new MyModule)
@@ -293,12 +317,12 @@ class DirectionSpec extends ChiselPropSpec with Matchers {
       // Chisel Emitter formats spacing a little differently than the
       // FIRRTL Emitter :-(
       val s = o.replace("{a", "{ a")
-      assert(s.contains("input inputVec : { a : UInt<1>, b : UInt<1>}[1]"))
-      assert(s.contains("input vecInput : { a : UInt<1>, b : UInt<1>}[1]"))
-      assert(s.contains("input vecInputFlipped : { a : UInt<1>, b : UInt<1>}[1]"))
-      assert(s.contains("output outputVec : { a : UInt<1>, b : UInt<1>}[1]"))
-      assert(s.contains("output vecOutput : { a : UInt<1>, b : UInt<1>}[1]"))
-      assert(s.contains("output vecOutputFlipped : { a : UInt<1>, b : UInt<1>}[1]"))
+      assert(s.contains("input inputVec : { a : UInt<1>, b : UInt<1>}[2]"))
+      assert(s.contains("input vecInput : { a : UInt<1>, b : UInt<1>}[2]"))
+      assert(s.contains("input vecInputFlipped : { a : UInt<1>, b : UInt<1>}[2]"))
+      assert(s.contains("output outputVec : { a : UInt<1>, b : UInt<1>}[2]"))
+      assert(s.contains("output vecOutput : { a : UInt<1>, b : UInt<1>}[2]"))
+      assert(s.contains("output vecOutputFlipped : { a : UInt<1>, b : UInt<1>}[2]"))
     } }
   }
 }