Patch VecInit.fill(0) invocation to successfully compile and yield a zero-width Vec (#3171)

Author: jared-barocsi

core/src/main/scala/chisel3/Aggregate.scala

@@ -777,7 +777,8 @@ object VecInit extends SourceInfoDoc {
 
   /** @group SourceInfoTransformMacro */
   def do_fill[T <: Data](n: Int)(gen: => T)(implicit sourceInfo: SourceInfo): Vec[T] =
-    apply(Seq.fill(n)(gen))
+    if (n == 0) { Wire(Vec(0, gen.cloneTypeFull)) }
+    else { apply(Seq.fill(n)(gen)) }
 
   /** Creates a new 2D [[Vec]] of length `n by m` composed of the result of the given
     * function applied to an element of data type T.

core/src/main/scala/chisel3/connectable/Connection.scala

@@ -2,7 +2,7 @@
 
 package chisel3.connectable
 
-import chisel3.{Aggregate, BiConnectException, Data, DontCare, InternalErrorException, RawModule}
+import chisel3.{Aggregate, BiConnectException, Data, DontCare, InternalErrorException, RawModule, Vec}
 import chisel3.internal.{BiConnect, Builder}
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.DefInvalid
@@ -204,6 +204,15 @@ private[chisel3] object Connection {
         // Recursive Case 4: non-empty orientations
         case (conAlign: NonEmptyAlignment, proAlign: NonEmptyAlignment) =>
           (conAlign.member, proAlign.member) match {
+            // Check for zero-width Vectors: both Vecs must be type equivalent, e.g.
+            // a UInt<8>[0] should not be connectable with a SInt<8>[0]
+            // TODO: This is a "band-aid" fix and needs to be unified with the existing logic in a
+            // more generalized and robust way
+            case (consumer: Vec[Data @unchecked], producer: Vec[Data @unchecked])
+                if (consumer.length == 0 && !consumer.typeEquivalent(producer)) =>
+              errors =
+                (s"Consumer (${consumer.cloneType.toString}) and producer (${producer.cloneType.toString}) have different types.") +: errors
+
             case (consumer: Aggregate, producer: Aggregate) =>
               matchingZipOfChildren(Some(conAlign), Some(proAlign)).foreach {
                 case (ceo, peo) =>

core/src/main/scala/chisel3/internal/BiConnect.scala

@@ -108,6 +108,14 @@ private[chisel3] object BiConnect {
           throw MismatchedVecException
         }
 
+        // Check for zero-width Vectors: both Vecs must be type equivalent, e.g.
+        // a UInt<8>[0] should not be connectable with a SInt<8>[0]
+        // TODO: This is a "band-aid" fix and needs to be unified with the existing logic in a
+        // more generalized and robust way, to account for things like Views
+        if (left_v.length == 0 && !left_v.typeEquivalent(right_v)) {
+          throw MismatchedException(left_v.cloneType.toString, right_v.cloneType.toString)
+        }
+
         val leftReified:  Option[Aggregate] = if (isView(left_v)) reifyToAggregate(left_v) else Some(left_v)
         val rightReified: Option[Aggregate] = if (isView(right_v)) reifyToAggregate(right_v) else Some(right_v)
 

core/src/main/scala/chisel3/internal/MonoConnect.scala

@@ -125,6 +125,14 @@ private[chisel3] object MonoConnect {
       case (sink_v: Vec[Data @unchecked], source_v: Vec[Data @unchecked]) =>
         if (sink_v.length != source_v.length) { throw MismatchedVecException }
 
+        // Check for zero-width Vectors: both Vecs must be type equivalent, e.g.
+        // a UInt<8>[0] should not be connectable with a SInt<8>[0]
+        // TODO: This is a "band-aid" fix and needs to be unified with the existing logic in a
+        // more generalized and robust way, to account for things like Views
+        if (sink_v.length == 0 && !sink_v.typeEquivalent(source_v)) {
+          throw MismatchedException(sink, source)
+        }
+
         val sinkReified:   Option[Aggregate] = if (isView(sink_v)) reifyToAggregate(sink_v) else Some(sink_v)
         val sourceReified: Option[Aggregate] = if (isView(source_v)) reifyToAggregate(source_v) else Some(source_v)
 

src/test/scala/chiselTests/Vec.scala

@@ -276,6 +276,48 @@ class VecSpec extends ChiselPropSpec with Utils {
     }
   }
 
+  property("0-width vectors should be compilable and have strongly-typed connection semantics") {
+    type ConnectOp = (Data, Data) => Unit
+
+    def test[T <: Data](gen: => T)(connect: ConnectOp) = {
+      val chirrtl = emitCHIRRTL(new Module {
+        val io = IO(new Bundle {
+          val out = Vec(0, UInt(8.W))
+        })
+
+        // Check if this is compilable, should pass
+        val zeroWidthVec = VecInit.fill(0)(gen)
+
+        // Check for strong-typed connections. Passes if gen is UInt(8.W),
+        // fails if gen is anything that isn't type equivalent
+        connect(io.out, zeroWidthVec)
+      })
+
+      // No need to check for SInt<8>[0] because the elaboration will fail for
+      // those cases
+      chirrtl should include(s"wire zeroWidthVec : UInt<8>[0]")
+    }
+
+    val connections: Seq[ConnectOp] = Seq(
+      (sink, source) => { sink := source },
+      (sink, source) => { sink <> source },
+      (sink, source) => { sink :#= source },
+      (sink, source) => { sink :<= source },
+      (sink, source) => { sink :>= source },
+      (sink, source) => { sink :<>= source }
+    )
+
+    for (connect <- connections) {
+      // Connect a UInt<8>[0] to an UInt<8>[0].
+      test(8.U(8.W))(connect)
+
+      // Attempt to connect a SInt<8>[0] to an UInt<8>[0].
+      a[ChiselException] should be thrownBy extractCause[ChiselException] {
+        test(8.S(8.W))(connect)
+      }
+    }
+  }
+
   property("Infering widths on huge Vecs should not cause a stack overflow") {
     ChiselStage.emitSystemVerilog(new HugeVecTester(10000))
   }