@@ -76,104 +76,26 @@ sealed abstract class Aggregate extends Data {
7676 private [core] override def connectFromBits (that : Bits )(implicit sourceInfo : SourceInfo ,
7777 compileOptions : CompileOptions ): Unit = {
7878 var i = 0
79- val bits = Wire (UInt (this .width), init = that) // handles width padding
79+ val bits = WireInit (UInt (this .width), that) // handles width padding
8080 for (x <- flatten) {
8181 x.connectFromBits(bits(i + x.getWidth - 1 , i))
8282 i += x.getWidth
8383 }
8484 }
8585}
8686
87- object Vec {
87+ trait VecFactory {
8888 /** Creates a new [[Vec ]] with `n` entries of the specified data type.
8989 *
9090 * @note elements are NOT assigned by default and have no value
9191 */
92- def apply [T <: Data ](n : Int , gen : T )(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): Vec [T ] = new Vec (gen.chiselCloneType, n)
93-
94- @ deprecated(" Vec argument order should be size, t; this will be removed by the official release" " chisel3"
95- def apply [T <: Data ](gen : T , n : Int )(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): Vec [T ] = new Vec (gen.chiselCloneType, n)
96-
97- /** Creates a new [[Vec ]] composed of elements of the input Seq of [[Data ]]
98- * nodes.
99- *
100- * @note input elements should be of the same type (this is checked at the
101- * FIRRTL level, but not at the Scala / Chisel level)
102- * @note the width of all output elements is the width of the largest input
103- * element
104- * @note output elements are connected from the input elements
105- */
106- def apply [T <: Data ](elts : Seq [T ]): Vec [T ] = macro VecTransform .apply_elts
107-
108- def do_apply [T <: Data ](elts : Seq [T ])(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): Vec [T ] = {
109- // REVIEW TODO: this should be removed in favor of the apply(elts: T*)
110- // varargs constructor, which is more in line with the style of the Scala
111- // collection API. However, a deprecation phase isn't possible, since
112- // changing apply(elt0, elts*) to apply(elts*) causes a function collision
113- // with apply(Seq) after type erasure. Workarounds by either introducing a
114- // DummyImplicit or additional type parameter will break some code.
115-
116- // Check that types are homogeneous. Width mismatch for Elements is safe.
117- require(! elts.isEmpty)
118- elts.foreach(requireIsHardware(_, " vec element"
119-
120- val vec = Wire (new Vec (cloneSupertype(elts, " Vec"
121-
122- // TODO: try to remove the logic for this mess
123- elts.head.direction match {
124- case ActualDirection .Input | ActualDirection .Output | ActualDirection .Unspecified =>
125- // When internal wires are involved, driver / sink must be specified explicitly, otherwise
126- // the system is unable to infer which is driver / sink
127- (vec zip elts).foreach(x => x._1 := x._2)
128- case ActualDirection .Bidirectional (_) =>
129- // For bidirectional, must issue a bulk connect so subelements are resolved correctly.
130- // Bulk connecting two wires may not succeed because Chisel frontend does not infer
131- // directions.
132- (vec zip elts).foreach(x => x._1 <> x._2)
92+ def apply [T <: Data ](n : Int , gen : T )(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): Vec [T ] = {
93+ if (compileOptions.declaredTypeMustBeUnbound) {
94+ requireIsChiselType(gen, " vec type"
13395 }
134- vec
96+ new Vec (gen.chiselCloneType, n)
13597 }
13698
137- /** Creates a new [[Vec ]] composed of the input [[Data ]] nodes.
138- *
139- * @note input elements should be of the same type (this is checked at the
140- * FIRRTL level, but not at the Scala / Chisel level)
141- * @note the width of all output elements is the width of the largest input
142- * element
143- * @note output elements are connected from the input elements
144- */
145- def apply [T <: Data ](elt0 : T , elts : T * ): Vec [T ] = macro VecTransform .apply_elt0
146-
147- def do_apply [T <: Data ](elt0 : T , elts : T * )(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): Vec [T ] =
148- apply(elt0 +: elts.toSeq)
149-
150- /** Creates a new [[Vec ]] of length `n` composed of the results of the given
151- * function applied over a range of integer values starting from 0.
152- *
153- * @param n number of elements in the vector (the function is applied from
154- * 0 to `n-1`)
155- * @param gen function that takes in an Int (the index) and returns a
156- * [[Data ]] that becomes the output element
157- */
158- def tabulate [T <: Data ](n : Int )(gen : (Int ) => T ): Vec [T ] = macro VecTransform .tabulate
159-
160- def do_tabulate [T <: Data ](n : Int )(gen : (Int ) => T )(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): Vec [T ] =
161- apply((0 until n).map(i => gen(i)))
162-
163- /** Creates a new [[Vec ]] of length `n` composed of the result of the given
164- * function repeatedly applied.
165- *
166- * @param n number of elements (amd the number of times the function is
167- * called)
168- * @param gen function that generates the [[Data ]] that becomes the output
169- * element
170- */
171- @ deprecated(" Vec.fill(n)(gen) is deprecated. Please use Vec(Seq.fill(n)(gen))" " chisel3"
172- def fill [T <: Data ](n : Int )(gen : => T ): Vec [T ] = macro VecTransform .fill
173-
174- def do_fill [T <: Data ](n : Int )(gen : => T )(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): Vec [T ] =
175- apply(Seq .fill(n)(gen))
176-
17799 /** Truncate an index to implement modulo-power-of-2 addressing. */
178100 private [core] def truncateIndex (idx : UInt , n : Int )(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): UInt = {
179101 val w = BigInt (n- 1 ).bitLength
@@ -184,6 +106,8 @@ object Vec {
184106 }
185107}
186108
109+ object Vec extends VecFactory
110+
187111/** A vector (array) of [[Data ]] elements. Provides hardware versions of various
188112 * collection transformation functions found in software array implementations.
189113 *
@@ -208,7 +132,7 @@ object Vec {
208132 * - when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined)
209133 * - Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier
210134 */
211- sealed class Vec [T <: Data ] private (gen : => T , val length : Int )
135+ sealed class Vec [T <: Data ] private [core] (gen : => T , val length : Int )
212136 extends Aggregate with VecLike [T ] {
213137 private [core] override def typeEquivalent (that : Data ): Boolean = that match {
214138 case that : Vec [T ] =>
@@ -326,6 +250,74 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
326250 }
327251}
328252
253+ object VecInit {
254+ /** Creates a new [[Vec ]] composed of elements of the input Seq of [[Data ]]
255+ * nodes.
256+ *
257+ * @note input elements should be of the same type (this is checked at the
258+ * FIRRTL level, but not at the Scala / Chisel level)
259+ * @note the width of all output elements is the width of the largest input
260+ * element
261+ * @note output elements are connected from the input elements
262+ */
263+ def apply [T <: Data ](elts : Seq [T ]): Vec [T ] = macro VecTransform .apply_elts
264+
265+ def do_apply [T <: Data ](elts : Seq [T ])(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): Vec [T ] = {
266+ // REVIEW TODO: this should be removed in favor of the apply(elts: T*)
267+ // varargs constructor, which is more in line with the style of the Scala
268+ // collection API. However, a deprecation phase isn't possible, since
269+ // changing apply(elt0, elts*) to apply(elts*) causes a function collision
270+ // with apply(Seq) after type erasure. Workarounds by either introducing a
271+ // DummyImplicit or additional type parameter will break some code.
272+
273+ // Check that types are homogeneous. Width mismatch for Elements is safe.
274+ require(! elts.isEmpty)
275+ elts.foreach(requireIsHardware(_, " vec element"
276+
277+ val vec = Wire (new Vec (cloneSupertype(elts, " Vec"
278+
279+ // TODO: try to remove the logic for this mess
280+ elts.head.direction match {
281+ case ActualDirection .Input | ActualDirection .Output | ActualDirection .Unspecified =>
282+ // When internal wires are involved, driver / sink must be specified explicitly, otherwise
283+ // the system is unable to infer which is driver / sink
284+ (vec zip elts).foreach(x => x._1 := x._2)
285+ case ActualDirection .Bidirectional (_) =>
286+ // For bidirectional, must issue a bulk connect so subelements are resolved correctly.
287+ // Bulk connecting two wires may not succeed because Chisel frontend does not infer
288+ // directions.
289+ (vec zip elts).foreach(x => x._1 <> x._2)
290+ }
291+ vec
292+ }
293+
294+ /** Creates a new [[Vec ]] composed of the input [[Data ]] nodes.
295+ *
296+ * @note input elements should be of the same type (this is checked at the
297+ * FIRRTL level, but not at the Scala / Chisel level)
298+ * @note the width of all output elements is the width of the largest input
299+ * element
300+ * @note output elements are connected from the input elements
301+ */
302+ def apply [T <: Data ](elt0 : T , elts : T * ): Vec [T ] = macro VecTransform .apply_elt0
303+
304+ def do_apply [T <: Data ](elt0 : T , elts : T * )(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): Vec [T ] =
305+ apply(elt0 +: elts.toSeq)
306+
307+ /** Creates a new [[Vec ]] of length `n` composed of the results of the given
308+ * function applied over a range of integer values starting from 0.
309+ *
310+ * @param n number of elements in the vector (the function is applied from
311+ * 0 to `n-1`)
312+ * @param gen function that takes in an Int (the index) and returns a
313+ * [[Data ]] that becomes the output element
314+ */
315+ def tabulate [T <: Data ](n : Int )(gen : (Int ) => T ): Vec [T ] = macro VecTransform .tabulate
316+
317+ def do_tabulate [T <: Data ](n : Int )(gen : (Int ) => T )(implicit sourceInfo : SourceInfo , compileOptions : CompileOptions ): Vec [T ] =
318+ apply((0 until n).map(i => gen(i)))
319+ }
320+
329321/** A trait for [[Vec ]]s containing common hardware generators for collection
330322 * operations.
331323 */
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