Bump for 100219 release

Author: ucbjrl

README.md

@@ -1,24 +1,24 @@
 ![Chisel 3](https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/chisel_logo.svg?sanitize=true)
 
-#
+---
 
 [![Join the chat at https://gitter.im/freechipsproject/chisel3](https://badges.gitter.im/freechipsproject/chisel3.svg)](https://gitter.im/freechipsproject/chisel3?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
 [![CircleCI](https://circleci.com/gh/freechipsproject/chisel3/tree/master.svg?style=shield)](https://circleci.com/gh/freechipsproject/chisel3/tree/master)
 [![GitHub tag (latest SemVer)](https://img.shields.io/github/tag/freechipsproject/chisel3.svg?label=release)](https://github.com/freechipsproject/chisel3/releases/latest)
 
 [**Chisel**](https://www.chisel-lang.org) is a hardware design language that facilitates **advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs**.
 Chisel adds hardware construction primitives to the [Scala](https://www.scala-lang.org) programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.
-This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the [Chisel Standard Library](https://www.chisel-lang.org/api/latest/chisel3/util/index.html), raising the level of abstraction in design while retaining fine-grained control.
+This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the [Chisel Standard Library](https://www.chisel-lang.org/api/latest/#chisel3.util.package), raising the level of abstraction in design while retaining fine-grained control.
 
 For more information on the benefits of Chisel see: ["What benefits does Chisel offer over classic Hardware Description Languages?"](https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages)
 
-Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](https://github.com/freechipsproject/firrtl), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations. 
+Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](https://github.com/freechipsproject/firrtl), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations.
 
 ## What does Chisel code look like?
 
 Consider an FIR filter that implements a convolution operation, as depicted in this block diagram:
 
-<img src="doc/images/fir_filter.svg?sanitize=true" width="512" />
+<img src="https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/fir_filter.svg?sanitize=true" width="512" />
 
 While Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such:
 
@@ -51,15 +51,15 @@ class FirFilter(bitWidth: Int, coeffs: Seq[UInt]) extends Module {
   for (i <- 1 until coeffs.length) {
     zs(i) := zs(i-1)
   }
-  
+
   // Do the multiplies
   val products = VecInit.tabulate(coeffs.length)(i => zs(i) * coeffs(i))
-  
+
   // Sum up the products
   io.out := products.reduce(_ + _)
 }
 ```
- 
+
 and use and re-use them across designs:
 ```scala
 val movingAverage3Filter = FirFilter(8.W, Seq(1.U, 1.U, 1.U))  // same 3-point moving average filter as before
@@ -72,11 +72,11 @@ val triangleFilter = FirFilter(8.W, Seq(1.U, 2.U, 3.U, 2.U, 1.U))  // 5-point FI
 
 ### Bootcamp Interactive Tutorial
 The [**online Chisel Bootcamp**](https://mybinder.org/v2/gh/freechipsproject/chisel-bootcamp/master) is the recommended way to get started with and learn Chisel.
-**No setup is required** (it runs in the browser), nor does it assume any prior knowledge of Scala.   
+**No setup is required** (it runs in the browser), nor does it assume any prior knowledge of Scala.
 
 ### Build Your Own Chisel Projects
 
-See [the setup instructions](SETUP.md) for how to set up your environment to run Chisel locally.
+See [the setup instructions](https://github.com/freechipsproject/chisel3/blob/master/SETUP.md) for how to set up your environment to run Chisel locally.
 
 When you're ready to build your own circuits in Chisel, **we recommend starting from the [Chisel Template](https://github.com/freechipsproject/chisel-template) repository**, which provides a pre-configured project, example design, and testbench. Follow the [chisel-template readme](https://github.com/freechipsproject/chisel-template) to get started.
 
@@ -88,7 +88,7 @@ resolvers ++= Seq(
 )
 libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.2-SNAPSHOT"
 libraryDependencies += "edu.berkeley.cs" %% "chisel-testers2" % "0.1-SNAPSHOT"
-``` 
+```
 
 ### Design Verification
 
@@ -107,12 +107,12 @@ These simulation-based verification tools are available for Chisel:
 - [**Gitter**](https://gitter.im/freechipsproject/chisel3), where you can ask questions or discuss anything Chisel
 - [**Website**](https://www.chisel-lang.org)
 
-If you are migrating from Chisel2, see [the migration guide on the wiki](https://github.com/ucb-bar/chisel3/wiki/Chisel3-vs-Chisel2).
+If you are migrating from Chisel2, see [the migration guide](https://www.chisel-lang.org/chisel3/chisel3-vs-chisel2.html).
 
 ### Data Types Overview
-These are the base data types for defining circuit wires (abstract types which may not be instantiated are greyed out):
+These are the base data types for defining circuit components:
 
-![Image](doc/images/type_hierarchy.png?raw=true)
+![Image](https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/type_hierarchy.svg?sanitize=true)
 
 ## Developer Documentation
 This section describes how to get started developing Chisel itself, including how to test your version locally against other projects that pull in Chisel using [sbt's managed dependencies](https://www.scala-sbt.org/1.x/docs/Library-Dependencies.html).

build.sbt

@@ -28,15 +28,15 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
   }
 }
 
-val defaultVersions = Map("firrtl" -> "1.2.0-RC2")
+val defaultVersions = Map("firrtl" -> "1.2-100219-SNAPSHOT")
 
 lazy val commonSettings = Seq (
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),
     Resolver.sonatypeRepo("releases")
   ),
   organization := "edu.berkeley.cs",
-  version := "3.2.0-RC2",
+  version := "3.2-100219-SNAPSHOT",
   autoAPIMappings := true,
   scalaVersion := "2.12.10",
   crossScalaVersions := Seq("2.12.10", "2.11.12"),

build.sc

@@ -35,7 +35,7 @@ object chiselCompileOptions {
 val crossVersions = Seq("2.12.10", "2.11.12")
 
 // Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
-val defaultVersions = Map("firrtl" -> "1.2.0-RC2")
+val defaultVersions = Map("firrtl" -> "1.2-100219-SNAPSHOT")
 
 def getVersion(dep: String, org: String = "edu.berkeley.cs") = {
   val version = sys.env.getOrElse(dep + "Version", defaultVersions(dep))
@@ -67,7 +67,7 @@ trait CommonChiselModule extends SbtModule {
 
 trait PublishChiselModule extends CommonChiselModule with PublishModule {
   override def artifactName = "chisel3"
-  def publishVersion = "3.2.0-RC2"
+  def publishVersion = "3.2-100219-SNAPSHOT"
 
   def pomSettings = PomSettings(
     description = artifactName(),

doc/images/Makefile

@@ -0,0 +1,12 @@
+.PHONY: all
+
+sources = \
+	type_hierarchy.dot
+
+all: $(sources:%.dot=%.svg) $(sources:%.dot=%.png)
+
+%.svg: %.dot
+	dot -Tsvg $< -o $@
+
+%.png: %.dot
+	dot -Tpng $< -o $@

doc/images/type_hierarchy.dot

@@ -0,0 +1,52 @@
+digraph TypeHierarchy {
+  graph [rankdir=BT bgcolor="transparent"]
+  { node [style=filled,shape=box]
+    { node [fillcolor="#f7fbff"]
+      Data
+      Element
+      Bits Num
+      Aggregate
+      VecLike
+      "Chisel Internal"
+    }
+    { node [fillcolor="#e5f5e0"]
+      Bool UInt SInt FixedPoint
+      Reset
+      AsyncReset
+      Record
+      Bundle
+      Vec
+      "Chisel Types"
+    }
+    { node [fillcolor="#fcbba1"]
+      "User Types"
+      Ellipsis [label="..."]
+    }
+
+    subgraph cluster_data_hierarchy {
+      color=transparent
+      Element
+      Bits Num
+      Reset
+      Bool UInt SInt FixedPoint
+      color=transparent
+      Aggregate
+      VecLike
+      Record
+      Bundle
+      Vec
+
+      {Aggregate Element} -> Data
+      {Bits Reset} -> Element
+      {FixedPoint SInt UInt} -> {Bits Num}
+      Bool -> {UInt Reset}
+      Ellipsis -> Bundle -> Record -> Aggregate
+      Vec -> {Aggregate VecLike}
+      AsyncReset -> {Element Reset}
+    }
+    subgraph cluster_legend {
+      label=Legend
+      "User Types" -> "Chisel Types" -> "Chisel Internal"
+    }
+  }
+}