DevMeeting - 2021-07-06

[jackkoenig]

2021-07-06 (No Meeting July 5th, US Holiday)

Outreach

• [jiuyang] CCC Shanghai
  • Editing video.
  • Waiting for videos from local conference (better quality of video for local presentations)
• [jiuyang] None resolved Q&A
  • 为什么在声明Wire/Reg的时候需要考虑Bundle的方向?(If a bundle is declared as an IO, it is necessary to specify all directions, but is it possible to declare Wire/Reg without considering the directions?) #1997
  • Why do modulus(%) and compare(===/<=/>=) operators combinations lead to firrtl.FirrtlInternalException? #1998

Pinned Items

• Priority PRs:
  • remove DefRegInit, change DefReg API with option definition. #1944: Unify Chisel internal IR of registers
    • WIP :( mybad(jiuyang)
  • Module with multiple memories have no readmem statements firrtl#2168: Annoying issue where Dedup breaks some Verilog customization annotations
    • Jared is working on this: Fix memory annotation deduplication firrtl#2286
  • Espresso Decoder #1964:
    • Depends on refactor github action #2003
  • refactor github action #2003 & Refactor tests #2004
    • Refactor CI and Tests
  • Update spec for Mux: Relax spec on 0-bit mux select, use SFC behavior firrtl#2285
    • Needs: Adam review
  • Problematic naming bug with Cat
    • Cat rename signal name if it doesn't suggest name yet #2010

Discussion 2 (no Discussion 1)

• Better way to communicate holidays to people who may attend this meeting
  • Send calendar invites on mailing list
    • Chisel-users? Revive chisel-dev?
  • Can we work it into the Github Discussions?
    • What notifications customization support is there?
• Moving these notes to Github Discussions?
  • Eg. DevMeeting - 2021-06-29/30 #1991
  • Can we convert to Markdown?
    • https://gsuite.google.com/marketplace/app/docs_to_markdown/700168918607
• 为什么在声明Wire/Reg的时候需要考虑Bundle的方向?(If a bundle is declared as an IO, it is necessary to specify all directions, but is it possible to declare Wire/Reg without considering the directions?) #1997
  • [jack] 3 things
    • Valid(...) is wrong, it assigns directions (Output) when it shouldn’t
      • Would like to fix this but it’s hard
      • Deprecate and remove (could add chisel3.Valid and deprecate chisel3.util.Valid)
      • Could add chisel3 internal way of marking “Is output but deprecated” and make Valid use it (basically tells you to wrap it in Output when used in directioned Bundles) -- basically could not have to deprecate chisel3.util.Valid but requires hacking on internals
    • It’s totally true that it’s weird to have to use Input/Output to coerce directions for an internal wire or reg, we could add NoDir(...) or .noDir or something
      • We could do this automatically for Reg or Memory but definitely should not for Wire
      • Should bidirectional registers be illegal (as they are?)
    • For internal signals, FIRRTL’s notion of “flipped” vs. “not flipped” makes more sense than our use of Input and Output, this is a bit of a regression from Chisel2 which allowed you to just .flip something

[jackkoenig]

I was able to generate this markdown directly from the Google Doc using https://gsuite.google.com/marketplace/app/docs_to_markdown/700168918607, check the source of the markdown to see the generated comment which includes what time I did the conversion

Pretty neat!