DevMeeting - 2021-08-02/03

[jackkoenig]

2021-08-02/03

Outreach

• CCC Shanghai 2021 videos are up
  • https://www.youtube.com/watch?v=2_WPFk8lriE&list=PL02hojk7ZTSeZOUqV8QND4dYbkTm3Ov2A

Updates

Pinned Items

• Priority PRs:

Discussion 1

• [schuyler] Context-sensitive Invalid: [FIRRTL] SFC Invalid Interpretation llvm/circt#1494
  • SFC has two interpretations of invalid that depend on context:
    • primop(_, invalid) means “invalid zero”
    • when with invalid default/validif means “undefined”
  • My concern is that the “zero interpretation” has caused a proliferation of Chisel code that relies on zero-initialization to work.
  • [schuyler] Proposal: differentiate this in chisel3 with foo := Undefined vs. foo := 0.U and turn on stricter checking that no foo := Undefined value hits a primop. Leave Chisel._ as-is and disable strict checking of undefined behavior.
    • [schuyler] (I really think the ship has sailed on this one, but the proposal is here to try and make this constructive.)
  • The handling of DontCare in Chisel/FIRRTL is analogous to X-optimistic behavior
  • [kevin] In optimizing “DontCare”, one source of “DontCare” can potentially take on multiple values. This could be a good thing, but could also be confusing
  • [schuyler] Undefined behavior can be very nice for the compiler because it can do whatever it wants
  • [kevin] What does the user want us to do?
    • We can’t make the compiler super aggressive without giving the user help
    • Maybe Schuyler is right that we should error if Undefined hits a primop, or maybe just when it hits an Output, or maybe a register, there’s a range of choices here
  • [schuyler] Any introduction of undefined behavior needs to have a justification
  • [jack] We should at least define and document what we’re currently doing and if we want to improve it from there, we can
• [schuyler] Disallow zero-bit muxes (again) in Spec: Update spec to disallow 0-bit mux sel firrtl#2305
• [kevin] allow optimizations to run before Verilog emission specific passes: add emitter for optimized low firrtl firrtl#2304
  • this will solve the dshlw issue that comes back to haunt us
  • demotes the Verilog backend to just another backend instead of having passes that are specific to that backend mixed into firrtl lowering + optimization
  • my personal goal is to allow the SMT backend to run after optimizations
• [jack] Chisel 3.4.4
  • Dedup attribute annos (backport #2297) firrtl#2306
  • And maybe a follow on of duplicating instead of erroring when they differ
• [jack] DataView Update
  • Almost done, API change from .viewAs(new MyType) to .viewAs[MyType] (except for Bundles which is now .viewAsSupertype(new MyType)
  • Alternatives to `.viewAsSupertype)
    • .viewUp
    • .viewAs
    • .upcast
    • .viewAsParent

Discussion 2

• [jack/chick] Memlib improvements: Identify specific memories to be implemented as SRAM cells ucb-art/rocket-dsp-utils#30
  • 1. Provide an annotation (and command-line option) to tell ReplSeqMems to ignore a memory
    • This could solve their issue in 2 ways:
      • Just leave the memories that should be flop arrays alone
      • Run ReplSeqMems twice to get 2 .conf files
    • Couple this with a transform to apply the cost function that Vladimir is asking for (mark all seqmems smaller than X)
      • [kevin] This should be an aspect instead
  • 2. Enhance the new built-in vlsi_mem_gen or user macrocompiler with parameters to flop arrays for small enough memories (too small for SRAMs to be the best implementation)
  • [schuyler] How CIRCT does this
    • Every memory gets “blackboxed” and then there’s a generator op for them that gets lowered
    • Ideally you would like a way to define how a memory gets lowered and you may want it to be different for each memory
    • [jack] One way of doing this is a cost function that encodes useful behavior (perhaps customizable to some extent)
  • [jack] Maybe worth opening up repl-seq-mems to more than just r,w and rw memories (ie. support more ports)
  • [kevin] What you want is an Aspect that lets you mark the memories with the technology that you want to use and that is respected by repl-seq-mems/vlsi_mem_gen/macrocompiler
• [kevin] There is another WOSET (https://woset-workshop.github.io)
  • People should submit Chisel and Chisel-related stuff!