DevMeeting - 2021-08-30/31

[jackkoenig]

2021-08-30/31

Outreach

• [martin] Chisel tutorial at FPL 2021 (8/31) https://cfaed.tu-dresden.de/fpl2021/workshops-and-tutorials
  • Afternoon Europe time
  • 57 registrants

Updates

• [jack] 3.4.4 Release - Working on it-ish, trying to get the flow working in Docker container
  • https://github.com/chipsalliance/api-config-chipsalliance/blob/fd5f974da8d2aec923e2c6bfc996b7f396f1881f/build.sc#L35-L58
    • Similar to sbt-ci-release

Pinned Items

• Priority PRs:

Discussion 1

• BlackBox migration is burden: BlackBox 3.4 -> 3.5 migration is burden  #2101
  • Could we migrate the “Has<implementation>” methods (eg. addResource) to be defined on BlackBoxes by default?
  • [jack] chisel3.BlackBox should not have io_ prefix so this is a bug in Chisel 3.5
  • [jiuyang] Can we stop having both BlackBox and ExtModule
    • BlackBox - only has io, drops io_ prefix
    • ExtModule - standard RawModule-style naming, prefixing, no required io_
    • [jack] we can, but need io_ prefix dropping functionality - proposal FlatIO using DataView (eg. val myPorts = FlatIO(new MyIntf))
• Signal Trace API makes verialtor being able to see internal signals Signal Trace API #2077
  • [kevin] how does this work with LowerTypes or Inline renaming?
    • [jiuyang] I’ll add more tests, but I think we should make LowerTypes and Inline be able to rename.(ask for some hard examples which cannot be handled by rename.)
      • [kevin] can you add some Modules with LowerTypes collisions to your test? see the LowerTypesSpec; also add an example of a module that is annotated to be inlined and make sure that the signal is correctly renamed when it goes into the Verilator file (see the InlineInstances tests).
        • Sure! Please comment on GitHub, so I can remember ;p
• Any comment on Single thread ucb-bar/chiseltest#371 ?
  • [ducky] Feedback
    • Make sure to make any new API experimental
    • Don’t muck with the internals too much to make this work, a small targeted fix please.
    • Don’t do a macro
• Diplomacy is re-maintained and refactored in http://github.com/chipsalliance/diplomacy
  • https://github.com/chipsalliance/diplomacy/issues TBD before publish
    • Need schedule a meeting to SiFive/UCB/XiangShan and other public users to discuss public/private API.
    • PLCT interns will contribute unittest and refine the documentation.
  • [jack] This is a Rocket-Chip Working Group (within CHIPS Alliance) repo and discussion should be centered there
• CDE is re-maintained in https://github.com/chipsalliance/api-config-chipsalliance
  • We need to publish this to Maven, so we can compile diplomacy then.
  • Henry has asked about a sonatype project, Jack to poke
• [kevin] introducing: a safe past construct
  • [jack] This is really cool.
  • [kevin] should we get this into Chisel proper?
  • [jack] Probably, but maybe let’s start in chiseltest and get people using it
• [kevin] trying to address a SyncReadMem.read bug (without fixing all the problems around this construct): SyncReadMem: fix bug with read(addr) and add some formal tests #2092
  • [jack] lol at this bug -- but fix looks good
  • This shouldn’t affect memory interface other than read port existing or not, if the port doesn’t exist, you’re probably getting bitten by this bug

Discussion 2

• [kevin] how can we graduate the new verification constructs? draft PR(turns out Kevin is teaching a section)
• [jack] Chisel 3.5
  • Bugs:
    • io_ prefix bug in BlackBox