ChiselSim status

[iamavolk]

Is ChiselSim a long-term replacement for ChiselTest, or it is intended to be integrated into svsim?

[seldridge]

Yes, ChiselSim is intended to be the long-term replacement for ChiselTest.

svsim is a separate library that solves different problems. svsim provides a way, from Scala, to compile Verilog using different backends (currently Verilator and VCS) and to apply stimulus to the compiled simulation binaries. This is a library used to build ChiselSim. However, they are complementary: ChiselSim provides a collection of APIs for simulating Chisel generators. svsim is the underlying infrastructure that does the simulation.