[Chiselsim] Exit simulation on $finish

[seldridge]

Currently, Chiselsim will only terminate if the simulator exits or the commands that it is trying to run are done. However, different simulators handle things like $finish (which the Chisel stop API lowers to) differently. E.g., consider the following example code:

module Foo();

initial begin
  $display("hello");
  $finish;
  $display("world");
  $finish;
end

endmodule

Compiling this with Verilator (verilator --binary Foo.sv && ./obj_dir/VFoo) will produce:

hello
- Foo.sv:5: Verilog $finish
world
- Foo.sv:7: Verilog $finish

If you run this with VCS (vcs Foo.sv && ./simv) will produce:

hello
$finish called from file "Foo.sv", line 5.
$finish at simulation time                    0

The problem here is that Verilator doesn't terminate. This seems to violate the Verilog spec, based on the snippet below:

That said, we can work around this by querying the VerilatedContext.getFinish() member function when in the run_simulation function (or elsewhere) to see if Verilator is reporting that the simulation is done.

This has two major benefits:

1. Simulations will actually exit instead of running until they hit a timeout. For ChiselSpec, this is currently 10k half-periods. We can exit simulations way earlier without wasting cycles.
2. We are hacking around this by post-processing the log looking for finish before an assert. All that checking logic can just go away if simulations actually terminate.