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literal.asUInt(width) always returns a Bool #4733
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Ha, I see the issue was me not using |
It's really hard to catch this sort of thing--we did create a macro for catching a similar case, e.g. chisel/macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala Line 357 in f2f3ade
We could try expanding that macro to catch this. Another option might be to define |
Yup, that makes sense. On one hand, this feels like a serious foot-gun, and is almost never intended ( |
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
Running this with
scala-cli
generates this result:What is the current behavior?
Running
x.asUInt(width)
always returns aBool
(the same happens if you changex
from aBigInt
to anInt
). If you change theout1 := x.asUInt(width)
line above to use the:<=
operator, you'll get this error:What is the expected behavior?
x.asUInt(width)
should return aUInt
of the specified width. I would expect the resulting Verilog to sayassign out1 = 8'hFF;
, likeout2
andout3
.Please tell us about your environment:
7.0.0-M2+432-486b55dc-SNAPSHOT
Other Information
What is the use case for changing the behavior?
This should match the behavior of
x.U(width.W)
.The text was updated successfully, but these errors were encountered: