Chisel v3.5.1

Highlights

• Generate Bundle.elements in the compiler plugin (#2306)
  The chisel3 compiler plugin can now generate Bundle.elements when -P:chiselplugin:genBundleElements is passed to Scalac (in SBT this is scalacOptions += "-P:chiselplugin:genBundleElements"). This results in a ~20-30% speedup for Chisel elaboration (excluding FIRRTL). This feature is disabled by default because it is a breaking change to implement elements for any non-final Bundle (a child class extending the given Bundle will rely on the old elementation via inheritance but will now call the newly implemented one in the superclass instead). Users who intend to publish libraries should not enable the feature until updating to Chisel 3.6. Everyone else should use it beginning in Chisel 3.5.1.
• Optional clock param for memory ports (#2333)
  Memories now bind clocks upon declaration of the memory and not just the ports. It is now a warning for a memory to use differing clocks at declaration time and port creation time unless the differing clock is passed explicitly to the port. For example:

val mem0 = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }
// This will warn because myClock differs from the implicit clock in scope ("clock")
val port0 = mem0(addr)

withClock(myClock) {
  val mem1 = SyncReadMem(4, UInt(8.W))
  // This will NOT warn because the clock is the same
  val port1 = mem1(addr)
}

val mem2 = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }
// This will NOT warn because we pass the clock explicitly at the point of port creation
val port2 = mem2(addr, otherClock)

Feature

• util: add GrayCode (#2353)
• Add Scala 2.13.8 to plugin cross-compilation (#2385)
• Improve error reporting (#2376)
• Expand supported val modifiers for @public (#2365)

BugFix

• Fix Compatibility Module io wrapping (#2355)
• Fix variable-name typo (#2397)
• FillInterleaved documentation: swap order of elements in Seq example (#2393)
• Fix Decoder bug for constant 0 and DC (#2363)