Chisel v3.5.3

Feature

• FlatIO (#2476)
  You can now create IO Bundles that do not have the name of the val as a prefix in the name of the resulting ports. See this Scastie (https://scastie.scala-lang.org/bPg2Kws2QY2rdVyYeENdxw) for an example.
• Enable Clock Invalidation (#2485)
• Generate a balanced tree with reduceTree (#2318)

Performance

• Micro-optimize Namespace.name (#2474)
• Micro-optimize String building in _computeName (#2472)
• Use var List instead of ListBuffer to save memory (#2465)
• Optimize memory use of naming prefixes (#2471)

BugFix

• Fix spurious warning from Bundle plugin (#2506)
• Fix error message for BlackBox without val io <: Record (#2504)
• Fix warning injected into user code by @chiselName (#2500)
• Allow creating memories without an implicit clock (#2494)
• verification: switch order of assert/assume and printf (#2484)
• Prevent FIRRTL bulk connects on BlackBox Bundles. (#2468)

Docs

• Clarify example in Printable (#2454)
• Fix small typos in doc comment (#2490)