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Chisel v5.0.0
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@jackkoenig jackkoenig released this 19 May 16:53
· 92 commits to 5.x since this release
v5.0.0
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Features

  • add MuxLookup.fromEnum (by @albertchen-sifive in #3071)
    add chisel3.util.MuxLookup.fromEnum
  • Fix FIRRTL spec emission and bump to spec 1.2.0 (by @jackkoenig in #3094)
    Fix emission of FIRRTL spec in emitted .fir. Now emitting FIRRTL version 1.2.0.
  • add curried MuxLookup.apply, deprecate old apply (by @albertchen-sifive in #3095)
    Add a new version of MuxLookup.apply that takes two parameter lists instead of one. This helps the scala compiler report better type errors.
  • Introduce svsim, a low level library for simulating SystemVerilog using Verilator and VCS. (by @GeorgeLyon in #3121)
    Added svsim, a new library for compiling and controlling SystemVerilog simulations in Scala using Verilator or VCS.
  • Add Simulator class for simulating Chisel modules with svsim (by @GeorgeLyon in #3136)
    • Added chisel3.simulator.Simulator for simulating Chisel modules with svsim
  • Use %[[]] format for ChiselAnnotations (by @seldridge in #3141)
  • Add EphemeralSimulator API (by @GeorgeLyon in #3142)
    • Introduce chisel3.simulator.EphemeralSimulator for ephemeral scenarios (such as scala-cli)
  • [svsim] Add option to wait for a VCS license if one is unavailable (by @GeorgeLyon in #3149)
  • intmodule exporting (by @darthscsi in #3148)
    Generate implementation-specific intirnsics.
  • Implement typeName API for stable Module names (by @jared-barocsi in #3130)
    This gives a flexible way to generate a stable name for a Chisel type, which is useful for problems like generating stable names for Modules and Queues
  • More Circt intrinsic wrappers (IsX, PlusArgsTest, PlusArgsValue) (by @darthscsi in #2958)
    Add support for Circt intrinsics.
  • Added .exclude to Connectable (by @azidar in #3172)
    Added .exclude mechanism on Connectable to enable never connecting to/from the marked fields using any connectable operator.
  • Add an annotation for specifying module port conventions (by @rwy7 in #3030)
  • Patch VecInit.fill(0) invocation to successfully compile and yield a zero-width Vec (by @jared-barocsi in #3171)
    Fix VecInit.fill(0) calls so that they compile and yield 0-width Vecs
  • Implement read-write memory accessors for SyncReadMem (backport #3190) (by @mergify[bot] in #3214)
    SyncReadMem.readWrite(address, writeData, enabled, isWrite) explicitly generates a read-write port that supports both read and write access to the memory.
  • Added more Connectable customization functions (backport #3227) (by @mergify[bot] in #3231)
    • Added .unsafe, a useful function on Connectable when users want a connection to "try its best but don't error".
  • Added .squeezeAllAs, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired.
  • Added .as, a useful function on Connectable when users to upcast the Scala type.
  • Connectable's now register erroneous connections (e.g. out of scope, unwritable sinks) to throw at end of elaboration
  • Allow DataView of Reset <=> [UInt<1>, AsyncReset] (backport #3181) (by @mergify[bot] in #3259)
  • Enable .viewAsSupertype to work on Records (backport #3267) (by @mergify[bot] in #3269)
    • Allow .viewAsSupertype to work on Records, with additional tests.
  • Ensure that errors in DataView show the problematic fields in a deterministic order.
  • Add Top-level parameterized reset type (backport #3276) (by @mergify[bot] in #3282)
    Add a HasParameterizedResetType to mix into Modules for their top level .reset

API Modification

  • [chisel5] git subtree add FIRRTL (by @seldridge in #2982)
  • [chisel5] Build FIRRTL in-tree, not published dependency (by @seldridge in #2983)
  • [chisel5] Remove SFC Compiler from FIRRTL Subtree (by @seldridge in #2984)
  • Removed innards and NotStrict for CompileOptions, and object Chisel (by @azidar in #3055)
    Removal of Chisel and the NotStrict compile options.
  • Remove compile options everywhere in Chisel internals. (by @azidar in #3056)
    Removed CompileOptions trait and associated code, as it is now unnecessary.
  • Remove LegacyModule and LegacyBlackBox (by @azidar in #3058)
    Removed LegacyModule and LegacyBlackBox. Users should instead now extend Module or BlackBox.
  • [nfc] Remove two unused SFC annotations (by @seldridge in #3102)
  • Remove ImplicitInvalidate (by @azidar in #3096)
    Remove ImplicitInvalidate - now users must explicitly assign DontCare to a module, at instantiation site, rather than this happening automatically because the module extended ImplicitInvalidate.
  • Remove reflectivelyFindIO, its unused (by @azidar in #3106)
  • Use %[[]] format for ChiselAnnotations (by @seldridge in #3141)
  • Fix Printf macro to catch s-interpolator usages in Scala 2.13 (by @adkian-sifive in #3143)
    Fix issue with printf macro error checking to catch s-interpolator usages in Scala 2.13
  • Remove _compatAutoWrapPorts no-op method (by @seldridge in #3164)
  • Emit annotations in the .fir file (by @jackkoenig in #3180)
    • Annotations are now emitted in the .fir file instead of in an auxiliary .anno.json file.
    • Serialized FIRRTL is now spec v2.0.0

API Deprecation

  • Deprecate ChiselStage$.elaborate (by @seldridge in #3160)
  • Deprecate Scala 2.12 in Chisel 3.6 through the compiler plugin (by @jared-barocsi in #3146)
    Deprecate Scala 2.12 for Chisel 3.6 and later versions

Performance

  • Make return value of Serializer.lazily lazy (by @jackkoenig in #3122)
    Reduce peak memory usage during .fir serialization by using lazy intermediate data structures.
  • Optimize BitPat equals, overlap, and cover (backport #3285) (by @mergify[bot] in #3288)

Fixes

  • Fix paper cut: bad message on calling litValue on Bundle containing DontCare (by @chick in #3043)
    There is now a better message when calling litValue on a Bundle that contains a DontCare
    that shows the Bundle and fields
  • Disallow --target-dir in ChiselStage$ (by @seldridge in #3063)
  • Remove deprecated CIRCT Options (by @seldridge in #3101)
  • Detect bound hardware when processing record elements (by @adkian-sifive in #3037)
    Using bound hardware as an Element for a Record will now throw a better error message
  • Actually fail on compilation errors and fix issue with older gcc versions (by @GeorgeLyon in #3132)
  • Fix naming for RHS of named unapply expressions (by @jackkoenig in #3163)
    This results in previously unnamed signals receiving names from the compiler plugin.
  • Report firtool version when firtool invocation errors (by @jackkoenig in #3174)
  • Revert checks for size 0 Vecs in connections (backport #3215) (by @mergify[bot] in #3216)
  • Fix Instantiate for Product parameters (backport #3210) (by @mergify[bot] in #3218)
    Instantiate previously erased type information for case classes and case objects which could result in incorrect behavior.

Documentation

  • Fix broken cookbook link (by @mwachs5 in #3073)
    Fix broken link in the cookbook about resolving UInt index mismatches
  • Update README, fix link to roadmap.md (by @jensengrey in #3091)
  • Update README.md, fix scala version support badge (by @seanjensengrey in #3119)
  • mdoc-ify intrinsic explanation (by @mwachs5 in #3152)
    Use mdoc to compile check the intrinsics explanation doc
  • update website and explanations menus to match eachother (by @mwachs5 in #3154)
    [Website] Update Explanation Menus to align with eachother
  • Fix three broken links in README.md Documentation section (by @aswaterman in #3166)
  • [CI] Add Release Notes Automation (by @jackkoenig in #3170)
  • Update README.md for Chisel 5 (by @jackkoenig in #3093)
  • [docs] Fix README logo and update versions (backport #3189) (by @mergify[bot] in #3193)
  • [fix] typo fix: chosen port of arbiter is not onehot but UInt (backport #3235) (by @mergify[bot] in #3261)
    Just a oneline fix to the comment of Arbiter chosen port

Dependency Updates

Build and Internal Changes

  • Chisel5 publishing (by @jackkoenig in #3044)
    Change published artifact from edu.berkeley.cs::chisel3 to org.chipsalliance::chisel. Set up automated publishing for 5.0-SNAPSHOT (to s01.oss.sonatype.org because Chips Alliance is a relatively new Sonatype organization). Merge old firrtl, chisel3-macros, chisel3-core, and chisel3 artifacts into a single artifact: chisel.
  • Update Mergify config and add generation script to this repository (by @jackkoenig in #3059)
  • [CI] Add integrationTests for execution-driven tests (by @jackkoenig in #3061)
  • Let sbt-dynver control the SBT version (by @jackkoenig in #3064)
    Change SNAPSHOT versioning scheme to be derived from git describe --tag. SNAPSHOTs will now be unique per push to main.
  • [CI] Do full unshallow clone for publish job (by @jackkoenig in #3069)
  • Use -std=c++11 for Verilator 5.0 support (by @seldridge in #3066)
  • Require unshallow clone to publish in SBT (by @jackkoenig in #3070)
  • Release Chisel v5.0.0-M1 (by @jackkoenig in #3087)
  • Simplify assertKnownWidth to Verilog test (by @seldridge in #3078)
  • Add VSCode devcontainer config (by @GeorgeLyon in #3083)
    Added standard config for VSCode dev containers that can get developers up and running with just Docker and VSCode. To use, simply open the repo in VSCode and choose "Rebuild and Reopen in Container".
  • More VSCode Devcontainer Improvements (by @GeorgeLyon in #3120)
  • Add SBT aliases for formatting including SBT files (by @jackkoenig in #3125)
  • Fix svsim to publish as part of unipublish (by @jackkoenig in #3127)
  • [devcontainer] Use CIRCT full source bundle instead of git (by @GeorgeLyon in #3139)
  • [CI] Revamp VecSpec (by @jackkoenig in #3159)
  • Added definition identifiers (by @azidar in #3135)
  • [CI] Require PRs to main to be labeled (by @jackkoenig in #3168)
  • [CI] Install firtool in the publish step (by @jackkoenig in #3176)
  • rewrite mill build scripts for chisel5. (by @sequencer in #3045)
  • Add Chisel Scala CLI template and automation (backport #3186) (by @mergify[bot] in #3194)
    Add a new Chisel template for using Chisel with Scala CLI, and adds some automation for uploading versions of this template on tagged releases (or workflow dispatch).
  • Add Data.findFirstTypeMismatch for better type checking (backport #3201) (by @mergify[bot] in #3205)
  • Read previousVersions for bincompat checking from a file (backport #3202) (by @mergify[bot] in #3208)
    We can now simply append versions as they are released to project/previous-versions.txt on relevant release branches. build.sbt also now contains instructions are how to waive binary compatibility breakages.
  • Enable push CI on all *.x branches (backport #3222) (by @mergify[bot] in #3223)
  • Improve SyncReadMem.read, .readWrite (backport #3221) (by @mergify[bot] in #3233)
  • Add workflow to automatically update binary compatibility checks (backport #3242) (by @mergify[bot] in #3246)
  • [5.x] Enable MiMa for v5.0.0-RC2 (by @chiselbot in #3248)
  • Add new workflow to fixup backports for release notes (backport #3252) (by @mergify[bot] in #3254)
    Improve backport automation so that release notes generation from backport PRs works properly.
  • SemanticDB requires private fields of case class to use "val" (backport #3270) (by @mergify[bot] in #3272)

Full Changelog: a005498...v5.0.0

Contributors

seanjensengrey, chick, and 15 other contributors
Assets 4
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