Chisel v3.6.0-M2

Note: These release notes are a work-in-progress

The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.

Try it out using this Scastie!

Highlights

• New implementation of the FIRRTL compiler
  • The FIRRTL compiler has been rewritten using MLIR.
  • Faster, better SystemVerilog emission, and a growing open-source community.
  • See CIRCT.
• Refined connection semantics (#2806)
  • Flexible yet safe.
  • See the documentation.
• Paths in source locators (#2791)
  • Source locators now include a distinguishing path from the root of your workspace.
  • This enables errors that point to your specific line of Chisel from MFC.

Deprecations

Note that many more deprecations are coming before the release of 3.6.0.

• Compatibility mode (import Chisel._)
• The Scala FIRRTL Compiler
• FixedPoint and related APIs
• Intervals and related APIs

Removals

Many APIs deprecated in Chisel 3.5 have been removed in Chisel 3.6.
This includes (but is not limited to):

• MultiIOModule (use Module)
• Parenthesized forms of zero-arity methods (eg. .asUInt() is removed, use .asUInt)
• RawModule.getPorts and chisel3.getModulePorts
• stop with non-zero return code

Performance Improvements

While there have been many performance improvements included in the Chisel 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 11% and 8% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.

• Optimize internal _ids datastructure to reduce its size: #2866
• Avoid creating unnecessary clones: #2611
  • eg. IO(Input(UInt(8.W))) will now create only a single UInt object instead of 3
• Removed reflective naming which removes an iteration of all Data within a Module: #2562
• Removed TransitNames and thus 2 vars from every HasId: #2604

Other Changes

• SystemVerilog Parameters for BlackBoxes are now emitted in alphabetical order

Migration

3.6.0-M2 includes everything from 3.5.5 and before. Some features are newly deprecated in 3.5.5 that are removed in 3.6.0-M2. Please bump to 3.5.5 before attempting to upgrade to 3.6.0-M2.

Additional Changes since 3.6.0-M1

• Bump CIRCT support (originally chisel-circt) from 0.5.0 to 0.8.0 (#2878)
• Fix string interpolation in util.exprimental.decode.bitset (#2882)
• Bugfix waiveEach not casting. Add waiveAllAs (#2894)
• [circt] Cleanup CIRCT error behavior (#2896, #2892)
• Take into account opaque members in squeeze functions (#2904)
• Clarify mismatched width error message (#2917)
• Fix bug where Flipped did not properly flip (#2919)
• Fix lazy cloning (#2921)

For complete changes since 3.6.0-M1, run

git log --oneline $(git merge-base origin/master v3.6.0-M1)..$(git merge-base origin/master v3.6.0-M2)

Chisel v3.6.0-M1

Note: These release notes are a work-in-progress

The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.

Try it out using this Scastie!

Highlights

• New implementation of the FIRRTL compiler
  • The FIRRTL compiler has been rewritten using MLIR.
  • Faster, better SystemVerilog emission, and a growing open-source community.
  • See CIRCT.
• Refined connection semantics (#2806)
  • Flexible yet safe.
  • See the documentation.
• Paths in source locators (#2791)
  • Source locators now include a distinguishing path from the root of your workspace.
  • This enables errors that point to your specific line of Chisel from MFC.

Deprecations

Note that many more deprecations are coming before the release of 3.6.0.

• Compatibility mode (import Chisel._)
• The Scala FIRRTL Compiler

Performance Improvements

While there have been many performance improvements included in the Chisel 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 11% and 8% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.

• Optimize internal _ids datastructure to reduce its size: #2866
• Avoid creating unnecessary clones: #2611
  • eg. IO(Input(UInt(8.W))) will now create only a single UInt object instead of 3
• Removed reflective naming which removes an iteration of all Data within a Module: #2562
• Removed TransitNames and thus 2 vars from every HasId: #2604

Other Changes

• SystemVerilog Parameters for BlackBoxes are now emitted in alphabetical order

Migration

3.6.0-M1 includes everything from 3.5.5 and before. Some features are newly deprecated in 3.5.5 that are removed in 3.6.0-M1. Please bump to 3.5.5 before attempting to upgrade to 3.6.0-M1.

Chisel v3.5.5

Highlights

• Add opt-in AutoCloneType for Records (#2781)
  Users are strongly encouraged to import chisel3.experimental.AutoCloneType and mix it in to their Records. Chisel will now print a warning when users implement cloneType themselves. It will be an error to implement cloneType yourself in Chisel 3.6.
• Add support for Scala 2.13.9, 2.13.10, and 2.12.17 (#2739, #2774)
• Support Printables as arguments to verification constructs (#2663)
• Add OpaqueType support to Records (#2662, #2783)

Feature

• Add ability to suppress enum cast warnings (#2671)
• Show equivalent warnings/errors only once (#2673)
• Add option to treat warnings as errors (#2676)
• Add generic Data equality (===) via extension method (#2669)
• Update toPrintable for Enums (#2707)
• Fix traceName module type to RawModule (#2765)
• Add traceNameV2 for backwards compat. of traceName (#2784)
• Add PartialDataView.supertype (#2826)
• Add DataMirror.getParent for getting parents of Modules (#2825)
• Improve Record.bind and Detect Records with unstable elements (#2829)
• Unify Chisel2 and chisel3 directionality (#2634)

Deprecation

• Warn on s-interpolator usage for assert, assume and printf (#2751)

Performance

• Replace some options with nullable vars (#2658)
• Use new lazy serialization in FIRRTL (#2741)
• Improve Record.bind and Detect Records with unstable elements (#2829)
• Change RawModule._commands to a VectorBuilder (#2839)

BugFix

• Backport .toTarget deprecation warning information (3.5.x) (#2697)
• Backport of eager error messages for annotations (3.5.x) (#2700)
• Wires should have source location information in firrtl (#2714)
• Remove incorrect clock warning on Mem.read (#2721)
• Add lexical scope checks to Assert, Assume and Printf (#2706)
• Make nested IsInstantiables with Data in them work (#2761)
• Don't modify the Builder prefix if reinvoking suggestName on a Data (#2789)
• Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795)
• Fix for <> to BlackBox.IO with Compatibility Bundles (#2801)
• Support Analog in DataView (#2782)
• Bugfix converter clearing flips (#2788)
• Add unit tests and fix for #2794 , add unit tests for #2773 (#2792)

Other

• Update video links for CCC 2022 (#2725)
• Change description for SInt unary negation (#2729)
• Publish an Initial Roadmap (#2804)

Chisel v3.5.4

Feature

• Add formatted Printable interpolator cf (#2528)
• Implement DecoupledIO.map utility (#2646)
• Add DataMirror isIO, isReg, isWire (#2601)
• Define leading '_' as API for creating temporaries (#2580)
• Implement trait for Chisel compiler to name arbitrary non-Data types (#2610)
• Support separately elaborating definition and instance in ChiselStage (#2512)
• New enhanced API for specifying Chisel to Firrtl Annotations (#2628)
• Add single argument Bits.extract (#2566)

Deprecation

• Deprecate chiselName and NoChiselNamePrefix trait (#2627)
• Deprecate TransitName (#2603)
• Add --warn:reflective-naming (#2561)
• Deprecate implicit .U() and .S() syntax for literal bit extracts (#2534)
• Deprecate accessing the name of non-hardware Data (#2550)
• Deprecate named arguments for methods moving to macros in 3.6 (#2530)

BugFix

• Make explicit copy constructors for ExplicitCompileOptions (#2629)
• Refactor TruthTable.apply and add factory method for Espresso (#2612)
• Handle varargs constructor arguments in Bundle plugin (#2585)
• Support VerificationStatement in the naming plugin (#2555)
• Support Vecs of empty Bundles (#2543)
• Support := views to DontCare (#2536)

Performance

• Micro-optimize BitPat.rawString (#2577)

Docs

• Add an Explanation chapter about Scala types vs Chisel Types vs Hardware (#2626)
• Fix broken link in interfaces-and-connections.md (#2607)
• Publish unidoc as ScalaDoc in chisel project (#2595)
• README: fix link to contributing.md (#2596)
• Make readme friendlier to beginners (#2586)
• [docs] Document partial register reset (#2582)
• Update CONTRIBUTING.md for cleanup process (#2523)

Other

• Update scala-compiler, scala-library, ... to 2.12.16 (#2618)
• CompileOptions: add and use emitStrictConnects (#2622)
• Add ImplicitInvalidate, to help migrate the explicitInvalidate compiler option (#2575)
• Added migration for inferModuleReset (#2571)

Chisel v3.5.3

Feature

• FlatIO (#2476)
  You can now create IO Bundles that do not have the name of the val as a prefix in the name of the resulting ports. See this Scastie (https://scastie.scala-lang.org/bPg2Kws2QY2rdVyYeENdxw) for an example.
• Enable Clock Invalidation (#2485)
• Generate a balanced tree with reduceTree (#2318)

Performance

• Micro-optimize Namespace.name (#2474)
• Micro-optimize String building in _computeName (#2472)
• Use var List instead of ListBuffer to save memory (#2465)
• Optimize memory use of naming prefixes (#2471)

BugFix

• Fix spurious warning from Bundle plugin (#2506)
• Fix error message for BlackBox without val io <: Record (#2504)
• Fix warning injected into user code by @chiselName (#2500)
• Allow creating memories without an implicit clock (#2494)
• verification: switch order of assert/assume and printf (#2484)
• Prevent FIRRTL bulk connects on BlackBox Bundles. (#2468)

Docs

• Clarify example in Printable (#2454)
• Fix small typos in doc comment (#2490)

Chisel v3.5.2

Feature

• Add scanLeftOr and scanRightOr utilies (#2407)
• Make TruthTable accept unknown input width (#2387)
• Hierarchy API: make Mems lookupable (#2404)
• Make Tuple2 Lookupable (#2372)
• Issue errors on out-of-range extracts when width is known (#2428)
• Overload getVerilogString to accept arguments (#2401)

BugFix

• Emit FIRRTL bulkconnects whenever possible (#2381)
• Support BlackBoxes in D/I (#2438)

Docs

• Add Verilog-chisel side by side Reference Page to Docs (#2323)
• [docs] Add Cookbook section on aliased Bundle fields (#2444)

Chisel v3.5.1

Highlights

• Generate Bundle.elements in the compiler plugin (#2306)
  The chisel3 compiler plugin can now generate Bundle.elements when -P:chiselplugin:genBundleElements is passed to Scalac (in SBT this is scalacOptions += "-P:chiselplugin:genBundleElements"). This results in a ~20-30% speedup for Chisel elaboration (excluding FIRRTL). This feature is disabled by default because it is a breaking change to implement elements for any non-final Bundle (a child class extending the given Bundle will rely on the old elementation via inheritance but will now call the newly implemented one in the superclass instead). Users who intend to publish libraries should not enable the feature until updating to Chisel 3.6. Everyone else should use it beginning in Chisel 3.5.1.
• Optional clock param for memory ports (#2333)
  Memories now bind clocks upon declaration of the memory and not just the ports. It is now a warning for a memory to use differing clocks at declaration time and port creation time unless the differing clock is passed explicitly to the port. For example:

val mem0 = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }
// This will warn because myClock differs from the implicit clock in scope ("clock")
val port0 = mem0(addr)

withClock(myClock) {
  val mem1 = SyncReadMem(4, UInt(8.W))
  // This will NOT warn because the clock is the same
  val port1 = mem1(addr)
}

val mem2 = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }
// This will NOT warn because we pass the clock explicitly at the point of port creation
val port2 = mem2(addr, otherClock)

Feature

• util: add GrayCode (#2353)
• Add Scala 2.13.8 to plugin cross-compilation (#2385)
• Improve error reporting (#2376)
• Expand supported val modifiers for @public (#2365)

BugFix

• Fix Compatibility Module io wrapping (#2355)
• Fix variable-name typo (#2397)
• FillInterleaved documentation: swap order of elements in Seq example (#2393)
• Fix Decoder bug for constant 0 and DC (#2363)

Chisel v3.5.0

Please see the porting guide for upgrading from Chisel 3.4.[1]

Chisel is built on top of FIRRTL so some FIRRTL changes can affect Chisel users, please see the FIRRTL v1.5.0 release notes as well.

Highlights

• Definition/Instance introduces a new experimental API for module instantiation that disentagles elaborating the definition (or implementation) from instantiation of a given module. This solves Chisel's longstanding reliance on "Deduplication" for generating Verilog with multiple instances of the same module. Please see the dedicated cookbook for more information. (#2045)
• DataView is an experimental mechanism for "viewing" Scala objects as a subtype of Data. Often, this is useful for viewing one subtype of Data, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. It enables some very powerful design patterns. Please see the documentation and cookbook for more information. (#1955)
• viewAsSuperType is a new mechanism for treating Bundles as if they were an instance of a parent type. It solves a longstanding issue with bulk connecting Bundles when there is an inheritance relationship between them [#661]. See the DataView cookbook for more details.
• Vec Literals provide a mechanism similar to BundleLiterals for creating literal Vecs. Please see the associated documentation for more details. (#1834)
• Seq/Tuple implicit conversions built on top of DataView make certain design patterns much more intuitive. These conversions are available by import chisel3.experimental.conversions._. See the related section of the DataView explanation for more details. (#2277)

Feature

• ExtModule now supports built in support for providing Verilog source (#1154)
• Naming improvements
  • When prefixing with a data, eagerly get local name (#1614)
  • Use Data refs for name prefixing with aggregate elements (#1616)
  • Added Force Name API (#1634)
• add new APIs to BitPat (#1819)
  • add Y, N, select, slice, and ## to BitPat.
  • Add toString method to BitPat
• Verification
  • Guard statements with module reset (#1891)
  • create and extend annotatable BaseSim class for verification nodes (#1968)
  • Make printf return BaseSim subclass so it can be named/annotated (#1992)
• Implement Espresso Decoder (#1914)(#1964)
• Add when.cond for getting the current when condition (#1694)
• add ShiftRegisters to expose register inside ShiftRegister.
• Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)
• Import memory files inline for Verilog generation (#1805)
• Make plugin autoclonetype always on (#1826)
• Add getVerilog in Chisel3 (#1921)
• Merge minimized table before return as a TruthTable (#1933)
• Add isOneOf method to ChiselEnum (#1966)
• Add BitSet API (#2211)
• Improve Data.toString (#2197)
• implement trace API. (#2077)
• Circular-shift (rotate) operations for UInt (#1140)
• Added flush capability to Queue (#2030)
• Added VecInit factory methods (fill,iterate)(#2059)
• Add multiple dimensions to VecInit fill and iterate (#2065)

API Changes

• Bundles can no longer be instantiated with bound hardware
• Bundles no longer can be instantiated with bound types
• Stop Emitting BlackBoxResourceAnno. This removes the - need for a FIRRTL compiler to grok the Java Resource API in order to handle BlackBoxResourceAnno. (#1954)
• Require the chisel3 compiler plugin (#2271)
  The chisel3 compiler plugin is now required. See https://github.com/chipsalliance/chisel3#build-your-own-chisel-projects for instructions on how to add it to your project.
• Refactor TruthTable to use Seq (#2217) -- this is changed from RC1
• Remove v3.4.0 version of autoNameRecursively (#2149)
• Remove .toBools (#2170)
• Remove ChiselExecutionOptions and HasChiselExecutionOptions (#2267)
• refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool]. (#2245) -- change from RC1
• Remove all Bundle cloneTypes and chiselRuntimeDeprecate its use (#2052)
  This is technically an API change but due to the new chisel3 compiler plugin requirement, it should not affect users

API Deprecations

• deprecate getPorts with modulePorts. (#1945)
• deprecate getModulePorts (#2284)
• Deprecate chisel3.internal.firrtl.Port (#2302)
  Deprecate (instead of removing) chisel3.internal.firrtl.Port. Fix deprecation warnings on public APIs that return this type and add ScalaDoc to replacement APIs.
• Deprecate chisel3.BackendCompilationUtilities (#2257)
• Deprecate computeName (#2192)
• Add nullary .fire to Valid and deprecate dummy version (#2156)
• Deprecate auto-application of empty argument lists to parameterless functions (#2124)
• Remove Deprecated APIs (#1730)
• remove 2.11 dedicated code. (#1744)
• 8a73362 Remove val io
• 7e4d1ee Update docs for the removal of val io and MultiIOModule
• 6c6ec71 Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModule

BugFix

• catch None.get in BitPat.apply(x: UInt): BitPat (#2276)
• Fix isACloneOf (#2205)
• Definition name index skipping with D/I (#2249)
• Fixed bug with unary minus on FixedPoint and Interval (#2154)
• Fix naming of unwrapped val io in Chisel.Modules (#2150)
• Fix chisel3 <> for Bundles that contain compatibility Bundles (#2031)(#2097)
• Fixing aspect injection context bug (#1874)
• Make it legal for concrete resets to drive abstract reset (#2018)
• Fix chisel3 <> for Bundles that contain compatibility Bundles.
• BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a
• Bundle defined in import Chisel._. (#2023)
• Fix higher-kinded types for autoclonetype (#2121)
• Fix bug where refs may not get set for Records (#1645)
• SeqUtils asUInt endian-ness: hi/lo instead of right/left (#1647)
• Bugfix - adding external modules was broken (#1649)
• Improve source locators for switch statements. (#1669)
• Fix RegInit of Bundle lits (#1688)
• Fix incorrect usage of emitFirrtl in test (#1817)
• Don't toggle top.cpp clock and reset on same cycle (#1820)
• Fix ShiftRegister with 0 delay. (#1903)
• implement model checking API for chiseltest (#1912)
• Fix CloneModuleAsRecord support for .toTarget (#1974)
• Fix aop.Select behavior for CloneModuleAsRecord (#1993)
• Fix ChiselEnum warnings and use Logger for warnings instead of println (#1999)
• Fix a bug causes incorrect pla generation when input is ?(#2113)

Dependency Bumping

• Update sbt to 1.5.7 (#2303)
• Update sbt to 1.5.6 (#2300)
• Update os-lib to 0.8.0 (#2301)
• Add scala 2.13.7 to plugin build list (#2228)
• Update sbt-mima-plugin to 1.0.1 (#2176)
• Update sbt-ci-release to 1.5.10 (#2183)
• Update sbt-scalafix to 0.9.33 (#2262)
• Update sbt-site to 1.4.1 (#1676)
• Update sbt-unidoc to 0.5.0
• Update sbt-mdoc to 2.2.24 (#2196)
• Update sbt-scoverage to 1.9.2 (#2229)
• Update sbt-ci-release to 1.5.9 (#2139)
• Update scalatest to 3.2.10 (#2140)

Miscellany

• Lazy .fir Emission, use BufferedCustomFileEmission in CircuitSerializationAnnotation (#2083)
• Also add newline to end of verilog modifier code blocks so that there is always a newline between code blocks and following material. (#2016)
• Provide user source locators in Builder.error errors (#1618)
• Enable Cat of Zero Element Vec (#1623)
• Make -e option work with ChiselStage methods (#1630)
• Remove Data.setRef assertion (#1654)
• For HasId.setRef, have first set win (with force override) (#1655)
• Refine autonaming to have more intuitive behavior (#1660)
• Add custom mdoc modifier for emitted Verilog (#1666)
• (encore) Builder: use LazyLogging.logger.warn to print elaboration message (#1670)
• 3bea616 [plugin] Disable BundleComponent by default, add option to enable
• a8d3238 [plugin] Stop autoclonetype stack traces when using plugin
• 1494231 [plugin] Implement autoclonetype in the compiler plugin
• e80e9a3 [plugin] Split ChiselComponent into its own file
• 0a0d7c6 Make it possible to GC Data instances
• 53b6204 Add no-plugin-tests for testing Chisel without the compiler plugin
• add helper function to convert chirrtl to firrtl. (#1854)
• b88ae1f Deprecate override_clock and override_reset in Module
• 5ece5aa Rename MultiIOModule to Module
• b96e7dd farewell Scala 2.11
  • use Seq.iter for oneline implementation. (#1723)
• Expose AnnotationSeq to Module. (#1731)
• Fix Mergify condition for labeling backports (#1742)
• Refactor EnumAnnotations and EnumFactory (#1747)
• Update reported width from div/rem to match FIRRTL results (#1748)
• Scala 2.13 support (#1751)
• Fix some typo and using foreach instead of map in BoringUtils (#1755)
• Fix incorrect comment in ScalaDoc (#1756)
• Bump to Scala 2.12.13 (#1766)
• Fix stack trace trimming across Driver/ChiselStage (#1771)
• Remove chisel3.stage.phases.DriverCompatibility (#1772)
• Add file line to source link from scaladoc (#1776)
• Fix conversions between DecoupledIO and IrrevocableIO (#1781)
• Aggregate: fix typo (#1789)
• [docs] MovingAverage3 => MovingSum3, The example in the README is a sum, not an average. (#2050)
• [docs] Fix broken mdoc (#1600)
• [docs] Move more docs (#1601)
• [docs] Move Chisel3 to SPDX license conventions (#1604)
• [docs] Small changes to memory doc (#2062)
• [docs] Fixed broken link to type h...

Chisel v3.5.0-RC2

Please see the porting guide for upgrading from Chisel 3.4.[1]

3.5.0-RC2 includes all changes from 3.5.0-RC1 so please see the RC1 release notes.

Chisel is built on top of FIRRTL so some FIRRTL changes can affect Chisel users, please see the FIRRTL 1.5.0-RC2 release notes as well.

Feature

• Add BitSet API (#2211)
• Implement DataViews for Seq and Tuple (#2277)
• Improve Data.toString (#2197)
• implement trace API. (#2077)
• Add type parameter support for @instantiable (#2206)
• Support @public on unimplemented vals (#2182)
• Circular-shift (rotate) operations for UInt (#1140)

API Changes

• Require the chisel3 compiler plugin (#2271)
  The chisel3 compiler plugin is now required. See https://github.com/chipsalliance/chisel3#build-your-own-chisel-projects for instructions on how to add it to your project.
• Refactor TruthTable to use Seq (#2217) -- this is changed from RC1
• Remove v3.4.0 version of autoNameRecursively (#2149)
• Remove .toBools (#2170)
• Remove ChiselExecutionOptions and HasChiselExecutionOptions (#2267)
• refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool]. (#2245) -- change from RC1
• Remove all Bundle cloneTypes and chiselRuntimeDeprecate its use (#2052)
  This is technically an API change but due to the new chisel3 compiler plugin requirement, it should not affect users

API Deprecations

• deprecate getModulePorts (#2284)
• Deprecate chisel3.internal.firrtl.Port (#2302)
  Deprecate (instead of removing) chisel3.internal.firrtl.Port. Fix deprecation warnings on public APIs that return this type and add ScalaDoc to replacement APIs.
• Deprecate chisel3.BackendCompilationUtilities (#2257)
• Deprecate computeName (#2192)
• Add nullary .fire to Valid and deprecate dummy version (#2156)
• Deprecate auto-application of empty argument lists to parameterless functions (#2124)

BugFix

• catch None.get in BitPat.apply(x: UInt): BitPat (#2276)
• Fix isACloneOf (#2205)
• Definition name index skipping with D/I (#2249)
• Fixed bug with unary minus on FixedPoint and Interval (#2154)
• Fix naming of unwrapped val io in Chisel.Modules (#2150)

Dependency Bumping

• Update sbt to 1.5.7 (#2303)
• Update sbt to 1.5.6 (#2300)
• Update os-lib to 0.8.0 (#2301)
• Add scala 2.13.7 to plugin build list (#2228)
• Update sbt-mima-plugin to 1.0.1 (#2176)
• Update sbt-ci-release to 1.5.10 (#2183)
• Update sbt-scalafix to 0.9.33 (#2262)
• Update sbt-site to 1.4.1 (#1676)
• Update sbt-unidoc to 0.5.0
• Update sbt-mdoc to 2.2.24 (#2196)
• Update sbt-scoverage to 1.9.2 (#2229)
• Update sbt-ci-release to 1.5.9 (#2139)
• Update scalatest to 3.2.10 (#2140)

Miscellany

• Improve exception message for aliased bundle fields (#2304)
• [docs] Add "Upgrading From Chisel 3.4 to 3.5" (#2275)
• Better MonoConnect error messages (#2248)
• Add support for dynamic indexing on Vec identity views (#2298)
• [docs] Update versioning appendix to include 3.5 (#2293)
• [docs] Remove body from minimizing output bits recipe (#2290)
• [docs] add minimizing output bits recipe (#2278)
• reduceTree() now operates on Seq (#2292)
• Add Hierarchy trait (#2204)
• add documentation to decoder. (#2254)
• Update bundles-and-vecs.md (#2173)
• Update experimental-features.md (#2175)
• Add field grouping ScalaDoc for ArbiterIO (#2208)
• Add field grouping ScalaDoc for other subclasses of Bundle (#2214)
• Exposing more APIs from D/I internals (#2220)
• Add Select APIs for Hierarchy package (#2210)
• Add java reflection to hierarchy (#2209)
• [docs] Improve tieoff Bundle to 0 (#2218)
• Fix GaloisLFSR comments (#2178)
• [docs] Remove workaround for fixed issue in mdoc crash blocks (#2147)
• Fix typos in documentation (#2141)
• verification: fix off by one error in deprecation message (#2135)
• make all verification statements publically available (#2089)

---

[1] You can contribute to the porting doc by opening PRs against https://github.com/chipsalliance/chisel3/blob/master/docs/src/appendix/upgrading-from-chisel-3-4.md

Chisel v3.5.0-RC1

Feature

• DataView is a mechanism for "viewing" Scala objects as a subtype of Data. Often, this is useful for viewing one subtype of Data, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. (#1955)
• Instance/Definition introduces a new experimental API for module instantiation that disentagles elaborating the definition (or implementation) from instantiation of a given module. This solves Chisel's longstanding reliance on "Deduplication" for generating Verilog with multiple instances of the same module. (#2045)
• ExtModule now supports built in support for providing Verilog source (#1154)
• Naming improvements
  • When prefixing with a data, eagerly get local name (#1614)
  • Use Data refs for name prefixing with aggregate elements (#1616)
  • Added Force Name API (#1634)
  • Bugfix - module name collision for injecting aspect (#1635)
• Support VecLiterals, useful as Vec initializers and in unit testing.(#1834)
• add new APIs to BitPat (#1819)
  • add Y, N, select, slice, and ## to BitPat.
  • Add toString method to BitPat
• Verification
  • Guard statements with module reset (#1891)
  • create and extend annotatable BaseSim class for verification nodes (#1968)
  • Make printf return BaseSim subclass so it can be named/annotated (#1992)
• Implement Espresso Decoder (#1914)(#1964)
• Add when.cond for getting the current when condition (#1694)
• add ShiftRegisters to expose register inside ShiftRegister.
• Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)
• Import memory files inline for Verilog generation (#1805)
• allowReflectiveAutoCloneType must work outside of Builder context (#1811)
• Make plugin autoclonetype always on (#1826)
• Add getVerilog in Chisel3 (#1921)
• Merge minimized table before return as a TruthTable (#1933)
• Add isOneOf method to ChiselEnum (#1966)
• Lazy .fir Emission, use BufferedCustomFileEmission in CircuitSerializationAnnotation (#2083)

API Modification

• Bundles can no longer be instantiated with bound hardware
• Bundles no longer can be instantiated with bound types
• Update core/src/main/scala/chisel3/Aggregate.scala
• deprecate getPorts with modulePorts. (#1945)
• Stop Emitting BlackBoxResourceAnno. This removes the - need for a FIRRTL compiler to grok the Java Resource API in order to handle BlackBoxResourceAnno. (#1954)
• Added flush capability to Queue (#2030)
• Added VecInit factory methods (fill,iterate)(#2059)
• Add multiple dimensions to VecInit fill and iterate (#2065)

Fix

• Fix chisel3 <> for Bundles that contain compatibility Bundles (#2031)(#2097)
• Fixing aspect injection context bug (#1874)
• Make it legal for concrete resets to drive abstract reset (#2018)
• Fix chisel3 <> for Bundles that contain compatibility Bundles.
• BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a
• Bundle defined in import Chisel._. (#2023)
• Fix higher-kinded types for autoclonetype (#2121)
• Fix bug where refs may not get set for Records (#1645)
• SeqUtils asUInt endian-ness: hi/lo instead of right/left (#1647)
• Bugfix - adding external modules was broken (#1649)
• Improve source locators for switch statements. (#1669)
• Fix RegInit of Bundle lits (#1688)
• Fix incorrect usage of emitFirrtl in test (#1817)
• Don't toggle top.cpp clock and reset on same cycle (#1820)
• Fix ShiftRegister with 0 delay. (#1903)
• implement model checking API for chiseltest (#1912)
• Fix CloneModuleAsRecord support for .toTarget (#1974)
• Fix aop.Select behavior for CloneModuleAsRecord (#1993)
• Fix ChiselEnum warnings and use Logger for warnings instead of println (#1999)
• Fix a bug causes incorrect pla generation when input is ?(#2113)

Documentation

• MovingAverage3 => MovingSum3, The example in the README is a sum, not an average. (#2050)
• Fix broken mdoc (#1600)
• Move more docs (#1601)
• Move Chisel3 to SPDX license conventions (#1604)
• Small changes to memory doc (#2062)
• Fixed broken link to type hierarchy diagram (#1611)
• Delete index.md (#1613)
• Fix crosslinks in mdoc. Can't use md suffix (#1640)
• Fix broken links in docs (#1643)
• Ignore tests using System.setSecurityManager (#1661)
• Update some README links to chipsalliance (#1673)
• readme: simplify sbt snippet and update to the latest stable release (#1686)
• Adding ChiselEnum Documentation Entry (#1795)
• Minor docs improvements (#1774)
• Reorganize website docs (#1806)
• Update the FAQ and add doc on versioning (#1827)
• Provide useful message on Vec.apply require (#1838)
• Fix formatting issue of links (#1844)
• Fix Gitter chat room link (#1848)
• Add documentation guide about memory initialization (#1850)
• Add "how to tie off to 0" to the Cookbook (#1857)
• Add a link to the Chisel book (#1872)
• Update type_hierarchy (#1979)
• Add example of stripping directions from type (#2074)

Testing and Continuous Integration

• Use requireIsChiselType check on Bundle elements
• Merge branch 'master' into autoclonetype2-bug-fixes
• Add bundle test for recursively bound aggregates (#2046)
• Switch to using Github Actions CI (#1690)
• Add seven segment display decoder test case (#1972)

Deprecations and other removals

• Remove Deprecated APIs (#1730)
• remove 2.11 dedicated code. (#1744)
• 8a73362 Remove val io
• 7e4d1ee Update docs for the removal of val io and MultiIOModule
• 6c6ec71 Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModule

Miscellany

• Also add newline to end of verilog modifier code blocks so that there is always a newline between code blocks and following material. (#2016)
• Change prefix stack to List[String] (#1617)
• Provide user source locators in Builder.error errors (#1618)
• Enable Cat of Zero Element Vec (#1623)
• Make -e option work with ChiselStage methods (#1630)
• Remove Data.setRef assertion (#1654)
• For HasId.setRef, have first set win (with force override) (#1655)
• Refine autonaming to have more intuitive behavior (#1660)
• Add custom mdoc modifier for emitted Verilog (#1666)
• (encore) Builder: use LazyLogging.logger.warn to print elaboration message (#1670)
• 3bea616 [plugin] Disable BundleComponent by default, add option to enable
• a8d3238 [plugin] Stop autoclonetype stack traces when using plugin
• 1494231 [plugin] Implement autoclonetype in the compiler plugin
• e80e9a3 [plugin] Split ChiselComponent into its own file
• 0a0d7c6 Make it possible to GC Data instances
• 53b6204 Add no-plugin-tests for testing Chisel without the compiler plugin
• add helper function to convert chirrtl to firrtl. (#1854)
• b88ae1f Deprecate override_clock and override_reset in Module
• 5ece5aa Rename MultiIOModule to Module
• b96e7dd farewell Scala 2.11
  • use Seq.iter for oneline implementation. (#1723)
• Expose AnnotationSeq to Module. (#1731)
• Fix Mergify condition for labeling backports (#1742)
• Refactor EnumAnnotations and EnumFactory (#1747)
• Update reported width from div/rem to match FIRRTL results (#1748)
• Scala 2.13 support (#1751)
• Fix some typo and using foreach instead of map in BoringUtils (#1755)
• Fix incorrect comment in ScalaDoc (#1756)
• Bump to Scala 2.12.13 (#1766)
• Fix stack trace trimming across Driver/ChiselStage (#1771)
• Remove chisel3.stage.phases.DriverCompatibility (#1772)
• Add file line to source link from scaladoc (#1776)
• Fix conversions between DecoupledIO and IrrevocableIO (#1781)
• Aggregate: fix typo (#1789)