Releases · chipsalliance/chisel

API Modification

(#1162) Move dontTouch, RawModule, and MultiIOModule out of experimental
The object dontTouch and the classes RawModule and MultiIOModule are promoted from experimental, implying their respective APIs are stable.

NOTE: There will be corresponding pull requests for the rest of the BIG10 that are impacted by these changes. This PR is required for the 3.2.0-RC1 release.

Fix

(#884) Inhibit aggressive resource file name mangling.
Minimize the name mangling of output resource files.

(#950) asBools, asBool, and chained apply on asBools

toBools -> asBools (toBools deprecated)
toBool -> asBool (toBool deprecated)
Fix chaining of apply after .asBools

(#995) Support DontCare in Mux and cloneSupertype
Support DontCare in Muxes

(#1036) Fix typo in link

(#1065) RawModule with no reset should be able to use withClock method.

(#1091) Fix treatment of Vec of Analog and Vec of Bundle of Analog

Feature

(#693) Incorporate lessons learned from latest publishing.

(#718) BoringUtils / Synthesizable Cross Module References

(#819) Add width utility functions to avoid incorrect usage of bare log2Ceil().
Add helper functions UnsignedBitsRequired and UnsignedWidthRequired to provide an alternative to the potentially incorrect usage of log2Ceil to calculate wire widths.

(#820) Bundle Literals Framework

Adds litToBigInt[Option], litToBoolean[Option], and litToDouble[Option] APIs. Deprecates previous isLit, litArg, litValue APIs, since those expose implementation details (LitArg), do not have Option variants, and may not return the type desired (BigInt/Boolean/Double).
[internal] literals now specified in Bindings, instead of in Data subtypes.
[internal] adds support for Bundle literals by introducing a Bundle literal binding that contains a map of leaf subelements to their literal values.
~~[internal] ids are now persistent through runs, necessary to allow Bundle literals outside a Builder context (otherwise, a new IdGen is created for each element, and the ids alias).~~
[internal] HasId hashcode and equals reverted to the Java Object defaults, which allows Data created outside a Builder context to be Map-indexable
[internal] Created a ChiselContext (like DynamicContext) for global operations (like _id creation) that can be done outside a Builder context.
[internal] lref/ref checks are more strict, but Bindings should ensure they don't trip, and cases where they do trip are likely to be FIRRTL errors.
[internal] Made accesses to DynamicContext more strict, and will throw an error in most cases. The exceptions are error logging (errors are discarded) and getting the current Module (which will return None if outside a Builder context).

Other notes:

Support for bundle literal extractors is not yet implemented (the TODO is intentional), proposal is to have litToBigInt[Option] do the right thing. Note that bundle subelement literals can be extracted.
Support for generating Bundle literal constructors by macro annotation will be in a future PR. This only provides the internal framework to support Bundle literals at all. A mockup of what the generated code could look like is in the Bundle literal test case.
litArg, litValue, isLit are deprecated globally, even in Chisel context. If anyone really cares (as in, this causes problems for someone), I can move those into the compatibility layer without the deprecation warning through implicit conversions.

(#829) Direct to firrtl
Directly translate from ChiselIR to FIRRTL without using the FIRRTL ANTLR Parser

(#833) [RFC] [Proposal] Programmatic Port Creation
Programmatic Port Creation

(#837) Add Emacs temporaries, backups to .gitignore

Add Emacs temporaries, backups to top-level .gitignore

(#838) Add instance inline API

Add instance inlining and flattening API

(#839) Correcting documentation errors in Arbiter.scala
Documentation Fixes in Arbiter.scala

(#840) Support for verilog memory loading.
The new annotation ChiselLoadMemoryAnnotation provides support for a memory to be
initialized during simulation. This uses the verilog $readmemh or $readmemb to provide a
text file with numeric values that can be loaded into the memory at the beginning of simulation.

Usage

Simple Memory

import chisel3.util.loadMemoryFromFile
...
// within a module
  val memory = Mem(memoryDepth, UInt(32.W))
  loadMemoryFromFile(memory, "mem_data")  // actual file name must be mem_data.txt

The default input format is hex using $readmemh. Binary text can be used instead via

  loadMemoryFromFile(memory, "mem_data", hexOrBinary = "b")

Memory can be an aggregation

class MemoryShape extends Bundle {
  val a = UInt(8.W)
  val b = SInt(8.W)
  val c = Bool()
}

class HasComplexMemory(memoryDepth: Int) extends Module {
 ...
  val memory = Mem(memoryDepth, new MemoryShape)
  loadMemoryFromFile(memory, "mem_data")

This memory will be broken up by the Firrtl compiler into three separate memories
memory_a, memory_b, memory_c
There must be a separate load file for each of these memories with the names
mem_data_a.txt, mem_data_b.txt, mem_data_c.txt

These files are not checked at compile time. It might be a good idea to give them full path names.

Input file format.

Standard verilog file compatible with $readmemh or $readmemb. Data has to exist in a text file. White space is allowed to improve readability, as well as comments in both single line and block. The numbers have to be stored as binary or hexadecimal values. The basic form of a memory file contains numbers separated by new line characters that will be loaded into the memory.

Implementation details

Using these annotations will create parallel modules using Chisel3's in-line black boxes and these parallel modules will be connected to the unaltered modules using verilog's bind statement.

(#842) Catch returns from within when blocks and provide an error message
Returns within when scopes used to give opaque error messages. Now they are caught earlier (with a stack trace) and explained in the error message.

(#843) Ignore eclipse metadata
Add Scala IDE (Eclipse) project metadata to .gitignore

(#846) Undeprecate log2Up and log2Down
Undo the deprecation of log2Up and log2Down until zero-width wires work.

(#850) Heterogeneous Vec (MixedVec)

Add a new dynamically indexable sequence like Vec that supports different underlying widths/types.

(#851) Bump recommended Verilator version to 3.922
Update the recommended Verilator version in README.md

(#853) Ensure names work for bundles and literals.
Ensure that instanceName can be called on any signal.

(#854) Fix use of read-only refs on rhs of connect in compatibility mode
Fix bug preventing the use of the output of aggregate Muxes on the rhs of a connection in compatibility mode.

(#855) Update versions and links in README

(#857) Revert removal of bit extraction const prop for literals

(#858) Bump to Scala 2.12.6 and make it the default.
Bump Scala 2.12 to 2.12.6 and make it the default.

(#862) Add support for Input() and Output() and test for same.
Input() and Output() have been available in Chisel2 since ucb-bar/chisel2-deprecated#734. Provide support for them in the compatibility package.

(#863) Update latest release reference.
Update latest release.

(#868) Cleanup implicit conversions
Removed implicitly added identity methods .data and .target from Data and DecoupledIO, and removed .x from String, Int, Long, BigInt, and Boolean

(#873) API Documentation Improvements

Improve API documentation using ScalaDoc groups

(#876) Minor tweaks to the style guide

(#877) [F764.1] Bump scopt from 3.6.0 -> 3.7.0

Bump scopt from 3.6.0 -> 3.7.0

(#880) [F764.2] Add dumpAnnotations method to Driver
Add dumpAnnotations method to Driver

(#887) Give type annotation to litOption.
The litOption field currently has no type that can be inferred. Some subtypes override it and give it a type, but the original declaration should have a type so things like bundles can override it.

(#888) Bump version reference in README.md

(#892) Strong enums

Added support for strongly-typed, self-annotating enums

(#894) Documentation tweaks

(#895) Add CODEOWNERS file

(#898) Change InlineSpec to expect "_" and not "$"

(#901) Add DataMirror.modulePorts
Add chisel3.experimental.DataMirror.modulePorts(module: BaseModule): Map[String, Data]

(#902) Modify ReadyValidIO noenq to set the data payload to DontCare.
Modified ReadyValidIO (also used in DecoupledIO) to set the data payload (.bits) to don't care when a no enqueue action (noenq) is called. This will clean up the frequently used idiom:

c.noenq
when( cond) {
  c.enq( data)
}

This currently needs to be written as:

c.noenq
c.bits := DontCare
when( cond) {
  c.enq( data)
}

It is possible that noenq was used like this in some existing code:

c.bits := 47.U
c.noenq
when( cond) {
  c.valid := true.B
}

If this was the case, then the PR will change the behavior of the circuit.
The comment for noenq is:

    /** Indicate no enqueue occurs. Valid is set to false, and bits are
      * connected to an uninitialized wire
      */

so it wasn't supposed to be used this way.

(#903) add HasBlackBoxPath to BlackBoxUtils.scala
Add HasBlackBoxPath to BlackBoxUtils.scala

(#912) Make BaseModule.name lazy

Make BaseModule.name lazy to enable better name parameterization, e.g., a module name can now be a function of a submodule name

(#913) Add BigInt / Int to Bool conversion (0.B, 1.B)

(#914) Fix LoadMemoryTransform for Instance Annotations

(#916) Turn off strong enum annotations

(#918) Fix Queue.io.count when entries=1
Queues with depth 1 now...

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Releases: chipsalliance/chisel

v3.2.0-RC1

API Modification

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