diff --git a/revision-history.yaml b/revision-history.yaml
index af36acba..fde94352 100644
--- a/revision-history.yaml
+++ b/revision-history.yaml
@@ -25,6 +25,7 @@ revisionHistory:
       - Add "enablelayer" to grammar.
       - Main module must be public.
       - Make commas mandatory, not whitespace.
+      - Update intrinsic module example to use a real intrinsic.
     abi:
       - Add ABI for public modules and filelist output.
       - Changed ABI for group and ref generated files.
diff --git a/spec.md b/spec.md
index efb0b162..a414db3e 100644
--- a/spec.md
+++ b/spec.md
@@ -240,13 +240,12 @@ FIRRTL version 4.0.0
 circuit Foo :
   public module Foo :
   ;; snippetbegin
-  intmodule MyIntrinsicModule_xhello_y64 :
-    input foo: UInt
-    output bar: UInt<4>
-    output baz: SInt<8>
-    intrinsic = IntrinsicName
-    parameter x = "hello"
-    parameter y = 42
+  intmodule LTLDelay:
+    input in: UInt<1>
+    output out: UInt<1>
+    intrinsic = circt_ltl_delay
+    parameter delay = 1
+    parameter length = 0
   ;; snippetend
 ```