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[major] Finalize FIRRTL 4.0.0 Public Modules #167
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3877e95
[major] Finalize FIRRTL 4.0.0 Public Modules
seldridge 2a25221
fixup! [major] Finalize FIRRTL 4.0.0 Public Modules
seldridge 247d67b
fixup! [major] Finalize FIRRTL 4.0.0 Public Modules
seldridge 966b8a4
fixup! [major] Finalize FIRRTL 4.0.0 Public Modules
seldridge 3582345
fixup! [major] Finalize FIRRTL 4.0.0 Public Modules
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These lines seem strange to me.
How can a circuit be empty if:
It feels like we're trying to document a quirk of the implementation. Maybe it would help to comment on the intention of these rules.
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Maybe there's a better way of putting this...
The PR is trying to make
public
mean the same thing for all modules. If a module is public then you get a Verilog module with ports following the port lowering ABI. If a module is private, anything can happen to the module. It may be optimized away, it may get inlined, it may be duplicated a million times, etc.The main module creates a discontinuity arising from making the main module implicitly
public
. If it is implicitly public, then either thepublic
keyword has no effect or the public keyword is mandatory (or the public keyword cannot be applied to the main module, but it is implicitlypublic
anyway).The language in this section is trying to say that a circuit which has no public modules can be optimized to produce no Verilog.
WDYT?
For full clarity, this is an intermediate step to FIRRTL 5. Currently you can get the "bag o' dags" representation in FIRRTL 4 with:
or perhaps the following, though FIRRTL compilers don't really handle this well right now:
In FIRRTL 5 we can drop the circuit entirely and just make this: