top: restore irq_o connection

chipsalliance · Jan 18, 2025 · c7bc89f · c7bc89f
1 parent 9f4b079
commit c7bc89f
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Showing 2 changed files with 8 additions and 7 deletions.
diff --git a/src/i3c_wrapper.sv b/src/i3c_wrapper.sv
@@ -112,9 +112,9 @@ module i3c_wrapper #(
 
     output logic peripheral_reset_o,
     input  logic peripheral_reset_done_i,
-    output logic escalated_reset_o
+    output logic escalated_reset_o,
 
-    // TODO: Add interrupts
+    output irq_o
 );
 
   // DAT memory export interface
@@ -218,7 +218,8 @@ module i3c_wrapper #(
 
       .peripheral_reset_o,
       .peripheral_reset_done_i,
-      .escalated_reset_o
+      .escalated_reset_o,
+      .irq_o
   );
 
   prim_ram_1p_adv #(

diff --git a/verification/cocotb/top/lib_i3c_top/test_interrupts.py b/verification/cocotb/top/lib_i3c_top/test_interrupts.py
@@ -70,7 +70,7 @@ async def test_rx_desc_stat(dut):
 
     # Setup
     i3c_controller, _, tb = await test_setup(dut)
-    irq = dut.xi3c_wrapper.i3c.irq_o
+    irq = dut.xi3c_wrapper.irq_o
 
     # Enable the interrupt
     csr = tb.reg_map.I3C_EC.TTI.INTERRUPT_ENABLE
@@ -106,7 +106,7 @@ async def test_tx_desc_stat(dut):
 
     # Setup
     i3c_controller, _, tb = await test_setup(dut)
-    irq = dut.xi3c_wrapper.i3c.irq_o
+    irq = dut.xi3c_wrapper.irq_o
 
     # Enable the interrupt
     csr = tb.reg_map.I3C_EC.TTI.INTERRUPT_ENABLE
@@ -154,7 +154,7 @@ async def test_ibi_done(dut):
 
     # Setup
     i3c_controller, _, tb = await test_setup(dut)
-    irq = dut.xi3c_wrapper.i3c.irq_o
+    irq = dut.xi3c_wrapper.irq_o
 
     target = i3c_controller.add_target(TARGET_ADDRESS)
     target.set_bcr_fields(ibi_req_capable=True, ibi_payload=True)
@@ -210,7 +210,7 @@ async def test_interrupt_force(dut, fields):
 
     # Setup
     i3c_controller, _, tb = await test_setup(dut, timeout_us=0.5)
-    irq = dut.xi3c_wrapper.i3c.irq_o
+    irq = dut.xi3c_wrapper.irq_o
 
     f_ena, f_force, f_sts = fields