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wrappper: use DIGITAL_IO_I3C define
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kgugala committed Jan 18, 2025
1 parent 075525c commit d118c6e
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Showing 4 changed files with 7 additions and 7 deletions.
6 changes: 3 additions & 3 deletions src/i3c_wrapper.sv
Original file line number Diff line number Diff line change
Expand Up @@ -93,8 +93,8 @@ module i3c_wrapper #(

`endif

// I3C input and output signals are exposed for the purpose of simulation with Verilator
`ifdef VERILATOR
// digital I3C input and output signals are exposed for the purpose of simulation
`ifdef DIGITAL_IO_I3C
input logic scl_i,
input logic sda_i,
output logic scl_o,
Expand Down Expand Up @@ -257,7 +257,7 @@ module i3c_wrapper #(
.cfg_i('0) // Unused
);

`ifdef VERILATOR
`ifdef DIGITAL_IO_I3C
assign scl_io2phy = scl_i;
assign sda_io2phy = sda_i;
assign scl_o = scl_phy2io;
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2 changes: 1 addition & 1 deletion testbench/Makefile
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Expand Up @@ -3,7 +3,7 @@
VCS = vcs
BUILD_DIR = $(I3C_ROOT_DIR)/testbench/build

BUILD_ARGS += +define+VERILATOR -full64 -sverilog
BUILD_ARGS += +define+DIGITAL_IO_I3C -full64 -sverilog
BUILD_ARGS += +libext+.sv +libext+.v
BUILD_ARGS += $(foreach dir,$(VERILOG_INCLUDE_DIRS),-y $(dir))
BUILD_ARGS += -debug_access+all +memcbk -timescale=1ns/1ps
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2 changes: 1 addition & 1 deletion testbench/tb.sv
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: Apache-2.0
`include "i3c_defines.svh"
`define VERILATOR
`define DIGITAL_IO_I3C

/*
Testbench
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4 changes: 2 additions & 2 deletions verification/cocotb/common.mk
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,7 @@ endif
# Enable processing of #delay statements
ifeq ($(SIM), verilator)
COMPILE_ARGS += --timing
COMPILE_ARGS += +define+DIGITAL_IO_I3C
COMPILE_ARGS += -Wall -Wno-fatal
COMPILE_ARGS += --x-assign unique --x-initial unique

Expand All @@ -50,10 +51,9 @@ ifeq ($(SIM), verilator)
endif

ifeq ($(SIM), vcs)
COMPILE_ARGS += +define+VERILATOR
COMPILE_ARGS += +libext+.sv +libext+.v
COMPILE_ARGS += +define+DIGITAL_IO_I3C
COMPILE_ARGS += $(foreach dir,$(VERILOG_INCLUDE_DIRS),-y $(dir))

COMPILE_ARGS += -debug_access+all +memcbk
SIM_ARGS += +dumpon
EXTRA_ARGS += +vcs+vcdpluson +vpdfile+dump.vpd
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