diff --git a/Makefile b/Makefile
index caa79430..7cfed24a 100644
--- a/Makefile
+++ b/Makefile
@@ -96,10 +96,18 @@ tests-axi: ## Run all verification/cocotb/* RTL tests for AXI bus configuration
 	$(MAKE) config CFG_NAME=axi
 	cd $(COCOTB_VERIF_DIR) && $(PYTHON) -m nox -R -t "axi" --no-venv --forcecolor
 
+tests-axi-ff: ## Run all verification/cocotb/* RTL tests for AXI bus configuration without coverage (input FF enabled)
+	$(MAKE) config CFG_NAME=axi_ff
+	cd $(COCOTB_VERIF_DIR) && $(PYTHON) -m nox -R -t "axi" --no-venv --forcecolor -- +MinSystemClockFrequency=200.0
+
 tests-ahb: ## Run all verification/cocotb/* RTL tests for AHB bus configuration without coverage
 	$(MAKE) config CFG_NAME=ahb
 	cd $(COCOTB_VERIF_DIR) && $(PYTHON) -m nox -R -t "ahb" --no-venv --forcecolor
 
+tests-ahb-ff: ## Run all verification/cocotb/* RTL tests for AHB bus configuration without coverage (input FF enabled)
+	$(MAKE) config CFG_NAME=ahb_ff
+	cd $(COCOTB_VERIF_DIR) && $(PYTHON) -m nox -R -t "ahb" --no-venv --forcecolor -- +MinSystemClockFrequency=200.0
+
 tests: tests-axi tests-ahb ## Run all verification/cocotb/* RTL tests fro AHB and AXI bus configurations without coverage
 
 # TODO: Enable full coverage flow
diff --git a/verification/cocotb/noxfile.py b/verification/cocotb/noxfile.py
index 99551f14..beb84832 100644
--- a/verification/cocotb/noxfile.py
+++ b/verification/cocotb/noxfile.py
@@ -25,6 +25,9 @@ def _verify(session, test_group, test_type, test_name, coverage=None, simulator=
     # session.install("-r", pip_requirements_path)
     test = VerificationTest(test_group, test_type, test_name, coverage)
 
+    # Translate session options to plusargs
+    plusargs = list(session.posargs)
+
     # Randomize seed for initialization of undefined signals in the simulation
     random.seed(time.time_ns())
     seed = random.randint(1, 10000)
@@ -40,21 +43,18 @@ def _verify(session, test_group, test_type, test_name, coverage=None, simulator=
             "COCOTB_RESULTS_FILE=" + test.filenames["xml"],
         ]
         if simulator == "verilator":
-            args.append(
-                "PLUSARGS="
-                + " ".join(
-                    [
-                        "+verilator+rand+reset+2",
-                        f"+verilator+seed+{seed}",
-                    ]
-                )
-            )
+            plusargs.extend([
+                "+verilator+rand+reset+2",
+                f"+verilator+seed+{seed}",
+            ])
         if coverage:
             args.append("COVERAGE_TYPE=" + coverage)
 
         if simulator:
             args.append("SIM=" + simulator)
 
+        args.append("PLUSARGS=" + " ".join(plusargs))
+
         session.run(
             *args,
             external=True,
diff --git a/verification/cocotb/top/lib_i3c_top/interface.py b/verification/cocotb/top/lib_i3c_top/interface.py
index 79557ca7..d62487f6 100644
--- a/verification/cocotb/top/lib_i3c_top/interface.py
+++ b/verification/cocotb/top/lib_i3c_top/interface.py
@@ -26,6 +26,16 @@ def __init__(self, dut: SimHandleBase) -> None:
         self.write_csr_field = self.busIf.write_csr_field
 
     async def setup(self, fclk=500.0):
+
+        # Limit the requested clock frequency if a limit is set via cocotb
+        # plusargs
+        fmin = cocotb.plusargs.get("MinSystemClockFrequency", None)
+        if fmin is not None:
+            fmin = float(fmin)
+            if fclk < fmin:
+                self.dut._log.warning(f"Enforcing min. system clock frequency of {fmin:.3f} MHz")
+                fclk = fmin
+
         await self.busIf.register_test_interfaces(fclk)
         await ClockCycles(self.clk, 20)
         await reset_n(self.clk, self.rst_n, cycles=5)