Merge pull request #3725 from Tang-Haojin/fix-circuitIdentity

Fix circuitIdentity in Xbars

Author: jerryz123

Diff for: src/main/scala/amba/ahb/Xbar.scala

@@ -21,7 +21,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
         requestKeys    = seq.flatMap(_.requestKeys).distinct,
         responseFields = BundleField.union(seq.flatMap(_.responseFields))) }
   ){
-    override def circuitIdentity = outputs == 1 && inputs == 1
+    override def circuitIdentity = outputs.size == 1 && inputs.size == 1
   }
 
   lazy val module = new Impl

Diff for: src/main/scala/amba/apb/Xbar.scala

@@ -21,7 +21,7 @@ class APBFanout()(implicit p: Parameters) extends LazyModule {
         requestKeys    = seq.flatMap(_.requestKeys).distinct,
         responseFields = BundleField.union(seq.flatMap(_.responseFields))) }
   ){
-    override def circuitIdentity = outputs == 1 && inputs == 1
+    override def circuitIdentity = outputs.size == 1 && inputs.size == 1
   }
 
   lazy val module = new Impl

Diff for: src/main/scala/amba/axi4/Xbar.scala

@@ -53,7 +53,7 @@ class AXI4Xbar(
       )
     }
   ){
-    override def circuitIdentity = outputs == 1 && inputs == 1
+    override def circuitIdentity = outputs.size == 1 && inputs.size == 1
   }
 
   lazy val module = new Impl

Diff for: src/main/scala/interrupts/Xbar.scala

@@ -15,7 +15,7 @@ class IntXbar()(implicit p: Parameters) extends LazyModule
       }.flatten)
     })
   {
-    override def circuitIdentity = outputs == 1 && inputs == 1
+    override def circuitIdentity = outputs.size == 1 && inputs.size == 1
   }
 
   lazy val module = new Impl
@@ -36,7 +36,7 @@ class IntSyncXbar()(implicit p: Parameters) extends LazyModule
       }.flatten)
     })
   {
-    override def circuitIdentity = outputs == 1 && inputs == 1
+    override def circuitIdentity = outputs.size == 1 && inputs.size == 1
   }
 
   lazy val module = new Impl