Merge pull request #3699 from chipsalliance/multi-rom

Support multiple ROMs

Author: jerryz123

Diff for: src/main/scala/devices/tilelink/BootROM.scala

@@ -13,6 +13,7 @@ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
 import freechips.rocketchip.resources.{Resource, SimpleDevice}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
+import freechips.rocketchip.util.{FileName, SystemFileName, ResourceFileName}
 
 import java.nio.ByteBuffer
 import java.nio.file.{Files, Paths}
@@ -22,7 +23,11 @@ case class BootROMParams(
   address: BigInt = 0x10000,
   size: Int = 0x10000,
   hang: BigInt = 0x10040, // The hang parameter is used as the power-on reset vector
-  contentFileName: String)
+  driveResetVector: Boolean = true,
+  appendDTB: Boolean = true,
+  name: String = "bootrom",
+  contentFileName: FileName = SystemFileName("./bootrom/bootrom.img")
+)
 
 class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
   resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
@@ -63,7 +68,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
   }
 }
 
-case class BootROMLocated(loc: HierarchicalLocation) extends Field[Option[BootROMParams]](None)
+case class BootROMLocated(loc: HierarchicalLocation) extends Field[Seq[BootROMParams]](Nil)
 
 object BootROM {
   /** BootROM.attach not only instantiates a TLROM and attaches it to the tilelink interconnect
@@ -73,27 +78,40 @@ object BootROM {
   def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation)
             (implicit p: Parameters): TLROM = {
     val tlbus = subsystem.locateTLBusWrapper(where)
-    val bootROMDomainWrapper = tlbus.generateSynchronousDomain("BootROM").suggestName("bootrom_domain")
+    val bootROMDomainWrapper = tlbus.generateSynchronousDomain(params.name).suggestName(s"${params.name}_domain")
 
     val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()
-    lazy val contents = {
-      val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
-      val rom = ByteBuffer.wrap(romdata)
-      rom.array() ++ subsystem.dtb.contents
+    val rom = params.contentFileName match {
+      case SystemFileName(fileName) => {
+        val romdata = Files.readAllBytes(Paths.get(fileName))
+        ByteBuffer.wrap(romdata).array()
+      }
+      case ResourceFileName(fileName) => {
+        val file = os.resource / os.RelPath(fileName.dropWhile(_ == '/'))
+        os.read.bytes(file)
+      }
+    }
+
+    lazy val contents = if (params.appendDTB) {
+      rom ++ subsystem.dtb.contents
+    } else {
+      rom
     }
 
     val bootrom = bootROMDomainWrapper {
       LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
     }
 
-    bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus, Some("BootROM")) := _ }
+    bootrom.node := tlbus.coupleTo(params.name){ TLFragmenter(tlbus, Some(params.name)) := _ }
     // Drive the `subsystem` reset vector to the `hang` address of this Boot ROM.
-    subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
-    InModuleBody {
-      val reset_vector_source = bootROMResetVectorSourceNode.bundle
-      require(reset_vector_source.getWidth >= params.hang.bitLength,
-        s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
-      bootROMResetVectorSourceNode.bundle := params.hang.U
+    if (params.driveResetVector) {
+      subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
+      InModuleBody {
+        val reset_vector_source = bootROMResetVectorSourceNode.bundle
+        require(reset_vector_source.getWidth >= params.hang.bitLength,
+          s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
+        bootROMResetVectorSourceNode.bundle := params.hang.U
+      }
     }
     bootrom
   }

Diff for: src/main/scala/subsystem/Configs.scala

@@ -1,3 +1,4 @@
+
 // See LICENSE.SiFive for license details.
 // See LICENSE.Berkeley for license details.
 
@@ -22,7 +23,7 @@ import freechips.rocketchip.resources.{
 import freechips.rocketchip.tile.{
   MaxHartIdBits, RocketTileParams, BuildRoCC, AccumulatorExample, OpcodeSet, TranslatorExample, CharacterCountExample, BlackBoxExample
 }
-import freechips.rocketchip.util.ClockGateModelFile
+import freechips.rocketchip.util.{ClockGateModelFile, SystemFileName}
 import scala.reflect.ClassTag
 
 case object MaxXLen extends Field[Int]
@@ -54,7 +55,7 @@ class BaseSubsystemConfig extends Config ((site, here, up) => {
     beatBytes = 8,
     blockBytes = site(CacheBlockBytes))
   // Additional device Parameters
-  case BootROMLocated(InSubsystem) => Some(BootROMParams(contentFileName = "./bootrom/bootrom.img"))
+  case BootROMLocated(InSubsystem) => Seq(BootROMParams(contentFileName = SystemFileName("./bootrom/bootrom.img")))
   case HasTilesExternalResetVectorKey => false
   case DebugModuleKey => Some(DefaultDebugModuleParams(64))
   case CLINTKey => Some(CLINTParams())
@@ -207,7 +208,7 @@ class WithIncoherentTiles extends Config((site, here, up) => {
 })
 
 class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
-  case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMFile))
+  case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName=SystemFileName(bootROMFile)))
 })
 
 class WithClockGateModel(file: String = "/vsrc/EICG_wrapper.v") extends Config((site, here, up) => {

Diff for: src/main/scala/util/package.scala

@@ -300,4 +300,10 @@ package object util {
   def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
   @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
   val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
+
+  trait FileName {
+    val fileName: String
+  }
+  case class SystemFileName(fileName: String) extends FileName
+  case class ResourceFileName(fileName: String) extends FileName
 }