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jerryz123jerryz123
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Merge pull request #3654 from Kevin99214/NewSubsystemConfigFragments
Adding new config fragments to Rocket-chip subsystem Config.scala
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Diff for: ‎src/main/scala/subsystem/Configs.scala

+209
Original file line numberDiff line numberDiff line change
@@ -309,6 +309,133 @@ class WithL1DCacheWays(ways: Int) extends Config((site, here, up) => {
309309
}
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})
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class WithL1ICacheECC(dataECC: String, tagECC: String) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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icache = tp.tileParams.icache.map(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC)))))
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case t => t
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}
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})
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class WithL1DCacheECC(dataECC: String, tagECC: String) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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dcache = tp.tileParams.dcache.map(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC), dataECCBytes=8))))
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case t => t
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}
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})
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class WithL1ICacheTLBSets(tlbsets: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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icache = tp.tileParams.icache.map(_.copy(nTLBSets = tlbsets))))
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case t => t
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}
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})
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class WithL1DCacheTLBSets(tlbsets: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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dcache = tp.tileParams.dcache.map(_.copy(nTLBSets = tlbsets))))
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case t => t
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}
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})
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class WithL1ICacheTLBWays(tlbways: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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icache = tp.tileParams.icache.map(_.copy(nTLBWays = tlbways))))
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case t => t
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}
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})
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class WithL1DCacheTLBWays(tlbways: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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dcache = tp.tileParams.dcache.map(_.copy(nTLBWays = tlbways))))
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case t => t
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}
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})
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class WithL1ICacheTLBBasePageSectors(pagesectors: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
362+
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
363+
icache = tp.tileParams.icache.map(_.copy(nTLBBasePageSectors = pagesectors))))
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case t => t
365+
}
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})
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class WithL1DCacheTLBBasePageSectors(pagesectors: Int) extends Config((site, here, up) => {
369+
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
370+
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
371+
dcache = tp.tileParams.dcache.map(_.copy(nTLBBasePageSectors = pagesectors))))
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case t => t
373+
}
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})
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class WithL1ICacheTLBSuperpages(superpages: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
378+
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
379+
icache = tp.tileParams.icache.map(_.copy(nTLBSuperpages = superpages))))
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case t => t
381+
}
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})
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class WithL1DCacheTLBSuperpages(superpages: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
386+
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
387+
dcache = tp.tileParams.dcache.map(_.copy(nTLBSuperpages = superpages))))
388+
case t => t
389+
}
390+
})
391+
392+
class WithRocketICacheRowBits(n: Int) extends Config((site, here, up) => {
393+
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
394+
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
395+
icache = tp.tileParams.icache.map(_.copy(rowBits = n))))
396+
case t => t
397+
}
398+
})
399+
400+
class WithRocketDCacheRowBits(n: Int) extends Config((site, here, up) => {
401+
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
402+
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
403+
dcache = tp.tileParams.dcache.map(_.copy(rowBits = n))))
404+
case t => t
405+
}
406+
})
407+
408+
class WithL1ICacheBlockBytes(bytes: Int = 64) extends Config((site, here, up) => {
409+
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
410+
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
411+
icache = tp.tileParams.icache.map(_.copy(blockBytes = bytes))))
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case t => t
413+
}
414+
})
415+
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class WithL1DCacheBlockBytes(bytes: Int = 64) extends Config((site, here, up) => {
417+
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
418+
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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dcache = tp.tileParams.dcache.map(_.copy(blockBytes = bytes))))
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case t => t
421+
}
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})
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class WithoutVM extends Config((site, here, up) => {
425+
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
427+
core = tp.tileParams.core.copy(useVM = false)))
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case t => t
429+
}
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})
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class WithCFlushEnabled extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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core = tp.tileParams.core.copy(haveCFlush = true)))
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case t => t
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}
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})
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class WithRocketCacheRowBits(n: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
@@ -427,6 +554,14 @@ class WithDefaultBtb extends Config((site, here, up) => {
427554
}
428555
})
429556

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class WithNoBtb extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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btb = None))
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case t => t
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}
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})
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430565
class WithFastMulDiv extends Config((site, here, up) => {
431566
case TilesLocated(location) => up(TilesLocated(location), site) map {
432567
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
@@ -436,6 +571,15 @@ class WithFastMulDiv extends Config((site, here, up) => {
436571
}
437572
})
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class WithCustomFastMulDiv(mUnroll: Int = 8, mEarlyOut: Boolean = true, dUnroll: Int = 1, dEarlyOut: Boolean = true, dEarlyOutGranularity: Int = 1) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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core = tp.tileParams.core.copy(mulDiv = Some(
578+
MulDivParams(mulUnroll = mUnroll, mulEarlyOut = mEarlyOut, divUnroll = dUnroll, divEarlyOut = dEarlyOut, divEarlyOutGranularity = dEarlyOutGranularity)))))
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case t => t
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}
581+
})
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class WithoutMulDiv extends Config((site, here, up) => {
440584
case TilesLocated(location) => up(TilesLocated(location), site) map {
441585
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
@@ -460,6 +604,32 @@ class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
460604
}
461605
})
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class WithBEU(addr: BigInt) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(beuAddr = Some(addr)))
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case t => t
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}
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})
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class WithRocketTileCDC(crossingType: ClockCrossingType = SynchronousCrossing()) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
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crossingType = crossingType
618+
))
619+
case other => other
620+
}
621+
})
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class WithSeperateClockReset extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
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forceSeparateClockReset = true
627+
))
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case other => other
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}
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})
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class WithRocketDebugROB(enable: Boolean = true, size: Int = 0) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
465635
case tp: RocketTileAttachParams if (enable) =>
@@ -477,6 +647,23 @@ class WithRocketCease(enable: Boolean = true) extends Config((site, here, up) =>
477647
}
478648
})
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class WithCoreClockGatingEnabled extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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core = tp.tileParams.core.copy(clockGate = true)
654+
))
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case t => t
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}
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})
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class WithDCacheClockGatingEnabled extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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dcache = tp.tileParams.dcache.map(_.copy(clockGate = true))))
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case t => t
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}
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})
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class WithNoSimulationTimeout extends Config((site, here, up) => {
481668
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
482669
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
@@ -576,6 +763,15 @@ class WithDefaultMemPort extends Config((site, here, up) => {
576763
idBits = 4), 1))
577764
})
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class WithCustomMemPort (base_addr: BigInt, base_size: BigInt, data_width: Int, id_bits: Int, maxXferBytes: Int) extends Config((site, here, up) => {
767+
case ExtMem => Some(MemoryPortParams(MasterPortParams(
768+
base = base_addr,
769+
size = base_size,
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beatBytes = data_width/8,
771+
idBits = id_bits,
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maxXferBytes = maxXferBytes), 1))
773+
})
774+
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class WithNoMemPort extends Config((site, here, up) => {
580776
case ExtMem => None
581777
})
@@ -588,6 +784,15 @@ class WithDefaultMMIOPort extends Config((site, here, up) => {
588784
idBits = 4))
589785
})
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class WithCustomMMIOPort (base_addr: BigInt, base_size: BigInt, data_width: Int, id_bits: Int, maxXferBytes: Int) extends Config((site, here, up) => {
788+
case ExtBus => Some(MasterPortParams(
789+
base = base_addr,
790+
size = base_size,
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beatBytes = data_width/8,
792+
idBits = id_bits,
793+
maxXferBytes = maxXferBytes))
794+
})
795+
591796
class WithNoMMIOPort extends Config((site, here, up) => {
592797
case ExtBus => None
593798
})
@@ -596,6 +801,10 @@ class WithDefaultSlavePort extends Config((site, here, up) => {
596801
case ExtIn => Some(SlavePortParams(beatBytes = 8, idBits = 8, sourceBits = 4))
597802
})
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804+
class WithCustomSlavePort (data_width: Int, id_bits: Int) extends Config((site, here, up) => {
805+
case ExtIn => Some(SlavePortParams(beatBytes = data_width/8, idBits = id_bits, sourceBits = 4))
806+
})
807+
599808
class WithNoSlavePort extends Config((site, here, up) => {
600809
case ExtIn => None
601810
})

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