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Support resource-file ROMs
1 parent de3f593 commit 337f2ab

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3 files changed

+27
-11
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3 files changed

+27
-11
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Diff for: src/main/scala/devices/tilelink/BootROM.scala

+17-8
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
1313
import freechips.rocketchip.resources.{Resource, SimpleDevice}
1414
import freechips.rocketchip.subsystem._
1515
import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
16+
import freechips.rocketchip.util.{FileName, SystemFileName, ResourceFileName}
1617

1718
import java.nio.ByteBuffer
1819
import java.nio.file.{Files, Paths}
@@ -25,7 +26,8 @@ case class BootROMParams(
2526
driveResetVector: Boolean = true,
2627
appendDTB: Boolean = true,
2728
name: String = "bootrom",
28-
contentFileName: String)
29+
contentFileName: FileName = SystemFileName("./bootrom/bootrom.img")
30+
)
2931

3032
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
3133
resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
@@ -79,14 +81,21 @@ object BootROM {
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val bootROMDomainWrapper = tlbus.generateSynchronousDomain(params.name).suggestName(s"${params.name}_domain")
8082

8183
val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()
82-
lazy val contents = {
83-
val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
84-
val rom = ByteBuffer.wrap(romdata)
85-
if (params.appendDTB) {
86-
rom.array() ++ subsystem.dtb.contents
87-
} else {
88-
rom.array()
84+
val rom = params.contentFileName match {
85+
case SystemFileName(fileName) => {
86+
val romdata = Files.readAllBytes(Paths.get(fileName))
87+
ByteBuffer.wrap(romdata).array()
8988
}
89+
case ResourceFileName(fileName) => {
90+
val file = os.resource / os.RelPath(fileName.dropWhile(_ == '/'))
91+
os.read.bytes(file)
92+
}
93+
}
94+
95+
lazy val contents = if (params.appendDTB) {
96+
rom ++ subsystem.dtb.contents
97+
} else {
98+
rom
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}
91100

92101
val bootrom = bootROMDomainWrapper {

Diff for: src/main/scala/subsystem/Configs.scala

+4-3
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
12
// See LICENSE.SiFive for license details.
23
// See LICENSE.Berkeley for license details.
34

@@ -22,7 +23,7 @@ import freechips.rocketchip.resources.{
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import freechips.rocketchip.tile.{
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MaxHartIdBits, RocketTileParams, BuildRoCC, AccumulatorExample, OpcodeSet, TranslatorExample, CharacterCountExample, BlackBoxExample
2425
}
25-
import freechips.rocketchip.util.ClockGateModelFile
26+
import freechips.rocketchip.util.{ClockGateModelFile, SystemFileName}
2627
import scala.reflect.ClassTag
2728

2829
case object MaxXLen extends Field[Int]
@@ -54,7 +55,7 @@ class BaseSubsystemConfig extends Config ((site, here, up) => {
5455
beatBytes = 8,
5556
blockBytes = site(CacheBlockBytes))
5657
// Additional device Parameters
57-
case BootROMLocated(InSubsystem) => Seq(BootROMParams(contentFileName = "./bootrom/bootrom.img"))
58+
case BootROMLocated(InSubsystem) => Seq(BootROMParams(contentFileName = SystemFileName("./bootrom/bootrom.img")))
5859
case HasTilesExternalResetVectorKey => false
5960
case DebugModuleKey => Some(DefaultDebugModuleParams(64))
6061
case CLINTKey => Some(CLINTParams())
@@ -207,7 +208,7 @@ class WithIncoherentTiles extends Config((site, here, up) => {
207208
})
208209

209210
class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
210-
case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMFile))
211+
case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName=SystemFileName(bootROMFile)))
211212
})
212213

213214
class WithClockGateModel(file: String = "/vsrc/EICG_wrapper.v") extends Config((site, here, up) => {

Diff for: src/main/scala/util/package.scala

+6
Original file line numberDiff line numberDiff line change
@@ -300,4 +300,10 @@ package object util {
300300
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
301301
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
302302
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
303+
304+
trait FileName {
305+
val fileName: String
306+
}
307+
case class SystemFileName(fileName: String) extends FileName
308+
case class ResourceFileName(fileName: String) extends FileName
303309
}

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