Merge pull request #3733 from Chelsea819/master

fix(SRAM.scala): change x_sel_1 RegNext to Reg(Bool())

Author: jerryz123

Diff for: src/main/scala/amba/axi4/SRAM.scala

@@ -75,8 +75,8 @@ class AXI4RAM(
     val w_full = RegInit(false.B)
     val w_id   = Reg(UInt())
     val w_echo = Reg(BundleMap(in.params.echoFields))
-    val r_sel1 = RegNext(r_sel0)
-    val w_sel1 = RegNext(w_sel0)
+    val r_sel1 = Reg(Bool())
+    val w_sel1 = Reg(Bool())
 
     when (in. b.fire) { w_full := false.B }
     when (in.aw.fire) { w_full := true.B }