Use new Chisel annotations API

tymcauley · tymcauley · commit 5d76b414c566 · 2025-03-09T16:56:06.000-07:00
The `ChiselAnnotation` API is going away in Chisel 7. Also in Chisel 7, this trait can be replaced by `chisel3.util.experimental.InlineInstanceAllowDedup`: chipsalliance/chisel#4508
diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
@@ -25,9 +25,7 @@ import freechips.rocketchip.util.SeqBoolBitwiseOps
 
 // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits
 trait InlineInstance { self: chisel3.experimental.BaseModule =>
-  chisel3.experimental.annotate(
-    new chisel3.experimental.ChiselAnnotation {
-      def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } )
+  chisel3.experimental.annotate(self)(Seq(firrtl.passes.InlineAnnotation(self.toNamed)))
 }
 
 class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p)

Original file line number	Diff line number	Diff line change
`@@ -25,9 +25,7 @@ import freechips.rocketchip.util.SeqBoolBitwiseOps`
`25`	`25`
`26`	`26`	`// TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits`
`27`	`27`	`trait InlineInstance { self: chisel3.experimental.BaseModule =>`
`28`		`- chisel3.experimental.annotate(`
`29`		`- new chisel3.experimental.ChiselAnnotation {`
`30`		`- def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } )`
	`28`	`+ chisel3.experimental.annotate(self)(Seq(firrtl.passes.InlineAnnotation(self.toNamed)))`
`31`	`29`	`}`
`32`	`30`
`33`	`31`	`class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p)`