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jerryz123jerryz123
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Merge pull request #3642 from chipsalliance/empty_diplomacy
Move clocking/resources out of diplomacy subpackage
2 parents f43041d + 4ac1529 commit 6d88d6c

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Diff for: ‎src/main/scala/amba/ahb/Parameters.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config.Parameters
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1010
import org.chipsalliance.diplomacy.nodes.BaseNode
1111

12-
import freechips.rocketchip.diplomacy.{AddressSet, Resource, RegionType, TransferSizes, Device, ResourceAddress, ResourcePermissions}
12+
import freechips.rocketchip.resources.{Resource, Device, ResourceAddress, ResourcePermissions}
13+
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
1314
import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase}
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import scala.math.{max, min}

Diff for: ‎src/main/scala/amba/ahb/SRAM.scala

+2-1
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@@ -7,7 +7,8 @@ import chisel3.util._
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import org.chipsalliance.cde.config.Parameters
88
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
99

10-
import freechips.rocketchip.diplomacy.{AddressSet, DiplomaticSRAM, HasJustOneSeqMem, RegionType, TransferSizes}
10+
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
11+
import freechips.rocketchip.resources.{DiplomaticSRAM, HasJustOneSeqMem}
1112
import freechips.rocketchip.tilelink.LFSRNoiseMaker
1213
import freechips.rocketchip.util.{MaskGen, DataToAugmentedData, SeqMemToAugmentedSeqMem, PlusArg}
1314

Diff for: ‎src/main/scala/amba/apb/Parameters.scala

+2-2
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@@ -9,8 +9,8 @@ import org.chipsalliance.cde.config.Parameters
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import org.chipsalliance.diplomacy.nodes.BaseNode
1111

12-
import freechips.rocketchip.diplomacy.{AddressSet, Resource, Device, RegionType, ResourceAddress, ResourcePermissions}
13-
12+
import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
13+
import freechips.rocketchip.resources.{Resource, Device, ResourceAddress, ResourcePermissions}
1414
import freechips.rocketchip.util.{BundleField, BundleKeyBase, BundleFieldBase}
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import scala.math.max

Diff for: ‎src/main/scala/amba/apb/SRAM.scala

+2-1
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@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config.Parameters
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import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
1111

12-
import freechips.rocketchip.diplomacy.{AddressSet, DiplomaticSRAM, HasJustOneSeqMem, RegionType}
12+
import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
13+
import freechips.rocketchip.resources.{DiplomaticSRAM, HasJustOneSeqMem}
1314
import freechips.rocketchip.tilelink.LFSRNoiseMaker
1415
import freechips.rocketchip.util.SeqMemToAugmentedSeqMem
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Diff for: ‎src/main/scala/amba/axi4/AsyncCrossing.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config.Parameters
99
import org.chipsalliance.diplomacy.nodes.{NodeHandle}
1010
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
1111

12-
import freechips.rocketchip.diplomacy.{AddressSet, AsynchronousCrossing}
12+
import freechips.rocketchip.diplomacy.{AddressSet}
13+
import freechips.rocketchip.prci.{AsynchronousCrossing}
1314
import freechips.rocketchip.tilelink.{TLRAMModel, TLFuzzer, TLToAXI4}
1415
import freechips.rocketchip.subsystem.CrossingWrapper
1516
import freechips.rocketchip.util.{ToAsyncBundle, FromAsyncBundle, AsyncQueueParams, Pow2ClockDivider}

Diff for: ‎src/main/scala/amba/axi4/Credited.scala

+2-1
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@@ -8,7 +8,8 @@ import org.chipsalliance.cde.config.Parameters
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99
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
1010

11-
import freechips.rocketchip.diplomacy.{AddressSet, CreditedCrossing}
11+
import freechips.rocketchip.diplomacy.{AddressSet}
12+
import freechips.rocketchip.prci.{CreditedCrossing}
1213
import freechips.rocketchip.subsystem.CrossingWrapper
1314
import freechips.rocketchip.tilelink._
1415
import freechips.rocketchip.util._

Diff for: ‎src/main/scala/amba/axi4/CrossingHelper.scala

+1-2
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,7 @@ package freechips.rocketchip.amba.axi4
55
import org.chipsalliance.cde.config.Parameters
66
import org.chipsalliance.diplomacy.lazymodule.{LazyScope}
77

8-
import freechips.rocketchip.diplomacy.{CrossingType, ClockCrossingType, NoCrossing, AsynchronousCrossing, RationalCrossing, SynchronousCrossing, CreditedCrossing}
9-
import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing}
8+
import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing, CrossingType, ClockCrossingType, NoCrossing, AsynchronousCrossing, RationalCrossing, SynchronousCrossing, CreditedCrossing}
109

1110
trait AXI4OutwardCrossingHelper {
1211
type HelperCrossingType <: CrossingType

Diff for: ‎src/main/scala/amba/axi4/Parameters.scala

+2-1
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@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config.Parameters
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1010
import org.chipsalliance.diplomacy.nodes.BaseNode
1111

12-
import freechips.rocketchip.diplomacy.{AddressSet, Resource, RegionType, TransferSizes, Device, ResourceAddress, ResourcePermissions, IdRange, BufferParams, IdMap, IdMapEntry, DirectedBuffers}
12+
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes, IdRange, BufferParams, IdMap, IdMapEntry, DirectedBuffers}
13+
import freechips.rocketchip.resources.{Resource, Device, ResourceAddress, ResourcePermissions}
1314
import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase, AsyncQueueParams, CreditedDelay}
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1516
import scala.math.max

Diff for: ‎src/main/scala/amba/axi4/RegisterRouter.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,8 @@ import org.chipsalliance.cde.config.Parameters
1010
import org.chipsalliance.diplomacy.ValName
1111
import org.chipsalliance.diplomacy.nodes.{SinkNode}
1212

13-
import freechips.rocketchip.diplomacy.{AddressSet, NoCrossing, TransferSizes}
13+
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
14+
import freechips.rocketchip.prci.{NoCrossing}
1415
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperInput, RegMapperParams, RegisterRouter}
1516
import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
1617
import freechips.rocketchip.util._

Diff for: ‎src/main/scala/amba/axi4/SRAM.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,8 @@ import org.chipsalliance.cde.config.Parameters
1010
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
1111

1212
import freechips.rocketchip.amba.AMBACorrupt
13-
import freechips.rocketchip.diplomacy.{AddressSet, DiplomaticSRAM, HasJustOneSeqMem, RegionType, TransferSizes}
13+
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
14+
import freechips.rocketchip.resources.{DiplomaticSRAM, HasJustOneSeqMem}
1415
import freechips.rocketchip.util.{BundleMap, SeqMemToAugmentedSeqMem}
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1617
/**

Diff for: ‎src/main/scala/amba/axi4/package.scala

+1-2
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,7 @@ package freechips.rocketchip.amba
55
import org.chipsalliance.diplomacy.ValName
66
import org.chipsalliance.diplomacy.nodes.{SimpleNodeHandle, OutwardNodeHandle, InwardNodeHandle}
77

8-
import freechips.rocketchip.diplomacy.HasClockDomainCrossing
9-
import freechips.rocketchip.prci.HasResetDomainCrossing
8+
import freechips.rocketchip.prci.{HasClockDomainCrossing, HasResetDomainCrossing}
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1110
/**
1211
* Provide bundles, adapters and devices etc for AMBA AXI4 protocol.

Diff for: ‎src/main/scala/amba/axis/Parameters.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,8 @@ import chisel3.util.{isPow2, log2Ceil}
77
import org.chipsalliance.cde.config.Parameters
88
import org.chipsalliance.diplomacy.nodes.BaseNode
99

10-
import freechips.rocketchip.diplomacy.{TransferSizes, Resource, IdRange}
10+
import freechips.rocketchip.diplomacy.{TransferSizes, IdRange}
11+
import freechips.rocketchip.resources.{Resource}
1112
import freechips.rocketchip.util.{BundleFieldBase, BundleField}
1213

1314

Diff for: ‎src/main/scala/devices/debug/Debug.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,8 @@ import org.chipsalliance.diplomacy.lazymodule._
1212
import freechips.rocketchip.amba.apb.{APBFanout, APBToTL}
1313
import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule}
1414
import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError}
15-
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice}
15+
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
16+
import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice}
1617
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode}
1718
import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}
1819
import freechips.rocketchip.rocket.{CSRs, Instructions}

Diff for: ‎src/main/scala/devices/tilelink/BootROM.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config._
99
import org.chipsalliance.diplomacy.bundlebridge._
1010
import org.chipsalliance.diplomacy.lazymodule._
1111

12-
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, Resource, SimpleDevice, TransferSizes}
12+
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
13+
import freechips.rocketchip.resources.{Resource, SimpleDevice}
1314
import freechips.rocketchip.subsystem._
1415
import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
1516

Diff for: ‎src/main/scala/devices/tilelink/BusBlocker.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,8 @@ import chisel3._
77
import org.chipsalliance.cde.config._
88
import org.chipsalliance.diplomacy.lazymodule._
99

10-
import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
10+
import freechips.rocketchip.diplomacy.{AddressSet}
11+
import freechips.rocketchip.resources.{SimpleDevice}
1112
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc}
1213
import freechips.rocketchip.tilelink.{TLBusWrapper, TLFragmenter, TLNameNode, TLNode, TLRegisterNode}
1314

Diff for: ‎src/main/scala/devices/tilelink/CLINT.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@ import chisel3.util._
88
import org.chipsalliance.cde.config._
99
import org.chipsalliance.diplomacy.lazymodule._
1010

11-
import freechips.rocketchip.diplomacy.{AddressSet, Resource, SimpleDevice}
11+
import freechips.rocketchip.diplomacy.{AddressSet}
12+
import freechips.rocketchip.resources.{Resource, SimpleDevice}
1213
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
1314
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
1415
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}

Diff for: ‎src/main/scala/devices/tilelink/ClockBlocker.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,8 @@ import chisel3._
66
import org.chipsalliance.cde.config._
77
import org.chipsalliance.diplomacy.lazymodule._
88

9-
import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
9+
import freechips.rocketchip.diplomacy.{AddressSet}
10+
import freechips.rocketchip.resources.{SimpleDevice}
1011
import freechips.rocketchip.prci.ClockAdapterNode
1112
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc}
1213
import freechips.rocketchip.tilelink.TLRegisterNode

Diff for: ‎src/main/scala/devices/tilelink/Deadlock.scala

+1
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ package freechips.rocketchip.devices.tilelink
55
import chisel3._
66
import org.chipsalliance.cde.config.Parameters
77
import freechips.rocketchip.diplomacy._
8+
import freechips.rocketchip.resources.{SimpleDevice}
89

910
/** Adds a /dev/null slave that does not raise ready for any incoming traffic.
1011
* !!! WARNING: This device WILL cause your bus to deadlock for as long as you

Diff for: ‎src/main/scala/devices/tilelink/DevNull.scala

+3-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,9 @@ package freechips.rocketchip.devices.tilelink
55
import org.chipsalliance.cde.config._
66
import org.chipsalliance.diplomacy.lazymodule._
77

8-
import freechips.rocketchip.diplomacy.{AddressSet, HasClockDomainCrossing, RegionType, SimpleDevice, TransferSizes}
8+
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
9+
import freechips.rocketchip.resources.{SimpleDevice}
10+
import freechips.rocketchip.prci.{HasClockDomainCrossing}
911
import freechips.rocketchip.tilelink.{TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
1012

1113
import freechips.rocketchip.tilelink.TLClockDomainCrossing

Diff for: ‎src/main/scala/devices/tilelink/Error.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ import chisel3.util._
88
import org.chipsalliance.cde.config._
99
import org.chipsalliance.diplomacy.lazymodule._
1010

11-
import freechips.rocketchip.diplomacy.SimpleDevice
11+
import freechips.rocketchip.resources.SimpleDevice
1212
import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions}
1313

1414
/** Adds a /dev/null slave that generates TL error response messages */

Diff for: ‎src/main/scala/devices/tilelink/MaskROM.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@ import chisel3.util._
88
import org.chipsalliance.cde.config._
99
import org.chipsalliance.diplomacy.lazymodule._
1010

11-
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, SimpleDevice, TransferSizes}
11+
import freechips.rocketchip.diplomacy.{RegionType, AddressSet, TransferSizes}
12+
import freechips.rocketchip.resources.{SimpleDevice}
1213
import freechips.rocketchip.subsystem.{Attachable, HierarchicalLocation, TLBusWrapperLocation}
1314
import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters, TLWidthWidget}
1415
import freechips.rocketchip.util.{ROMConfig, ROMGenerator}

Diff for: ‎src/main/scala/devices/tilelink/PhysicalFilter.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@ import chisel3.util._
88
import org.chipsalliance.cde.config._
99
import org.chipsalliance.diplomacy.lazymodule._
1010

11-
import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
11+
import freechips.rocketchip.diplomacy.{AddressSet}
12+
import freechips.rocketchip.resources.{SimpleDevice}
1213
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}
1314
import freechips.rocketchip.tilelink.{TLAdapterNode, TLMessages, TLPermissions, TLRegisterNode}
1415

Diff for: ‎src/main/scala/devices/tilelink/Plic.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@ import chisel3.util._
99
import org.chipsalliance.cde.config._
1010
import org.chipsalliance.diplomacy.lazymodule._
1111

12-
import freechips.rocketchip.diplomacy.{AddressSet, Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
12+
import freechips.rocketchip.diplomacy.{AddressSet}
13+
import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
1314
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
1415
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
1516
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}

Diff for: ‎src/main/scala/devices/tilelink/TestRAM.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@ import chisel3.util._
88
import org.chipsalliance.cde.config._
99
import org.chipsalliance.diplomacy.lazymodule._
1010

11-
import freechips.rocketchip.diplomacy.{AddressSet, MemoryDevice, RegionType, TransferSizes}
11+
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
12+
import freechips.rocketchip.resources.{MemoryDevice}
1213
import freechips.rocketchip.tilelink.{TLDelayer, TLFuzzer, TLManagerNode, TLMessages, TLRAMModel, TLSlaveParameters, TLSlavePortParameters}
1314

1415
// Do not use this for synthesis! Only for simulation.

Diff for: ‎src/main/scala/devices/tilelink/Zero.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@ import chisel3.util._
88
import org.chipsalliance.cde.config._
99
import org.chipsalliance.diplomacy.lazymodule._
1010

11-
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, SimpleDevice}
11+
import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
12+
import freechips.rocketchip.resources.{SimpleDevice}
1213
import freechips.rocketchip.tilelink.TLMessages
1314

1415
/** This /dev/null device accepts single beat gets/puts, as well as atomics.

Diff for: ‎src/main/scala/diplomacy/AddressRange.scala

-18
Original file line numberDiff line numberDiff line change
@@ -60,21 +60,3 @@ object AddressRange
6060
def subtract(from: Seq[AddressRange], take: Seq[AddressRange]): Seq[AddressRange] =
6161
take.foldLeft(from) { case (left, r) => left.flatMap { _.subtract(r) } }
6262
}
63-
64-
case class AddressMapEntry(range: AddressRange, permissions: ResourcePermissions, names: Seq[String]) {
65-
val ResourcePermissions(r, w, x, c, a) = permissions
66-
67-
def toString(aw: Int) = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s".format(
68-
range.base,
69-
range.base+range.size,
70-
if (a) 'A' else ' ',
71-
if (r) 'R' else ' ',
72-
if (w) 'W' else ' ',
73-
if (x) 'X' else ' ',
74-
if (c) 'C' else ' ',
75-
names.mkString(", "))
76-
77-
def toJSON = s"""{"base":[${range.base}],"size":[${range.size}],""" +
78-
s""""r":[$r],"w":[$w],"x":[$x],"c":[$c],"a":[$a],""" +
79-
s""""names":[${names.map('"'+_+'"').mkString(",")}]}"""
80-
}

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