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Merge pull request #3651 from chipsalliance/ptw_leaf
PTW: traverse check GPA bits higher than HGATP mode only if leaf
2 parents ea9979b + 949ca21 commit 79626c0

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Diff for: src/main/scala/rocket/PTW.scala

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Original file line numberDiff line numberDiff line change
@@ -695,7 +695,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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when (do_both_stages && !stage2) { do_switch := true.B }
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count := count + 1.U
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}.otherwise {
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val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.v && pte.reserved_for_future === 0.U && invalid_gpa)
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val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa)
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val ae = pte.v && invalid_paddr
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val pf = pte.v && pte.reserved_for_future =/= 0.U
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val success = pte.v && !ae && !pf && !gf
@@ -723,7 +723,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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}
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resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table()
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resp_ae_final := ae
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resp_ae_final := ae && pte.leaf()
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resp_pf := pf && !stage2
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resp_gf := gf || (pf && stage2)
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resp_hr := !stage2 || (!pf && !gf && pte.ur())

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