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Support multiple ROMs
1 parent 72690b0 commit 8a68214

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2 files changed

+20
-11
lines changed

2 files changed

+20
-11
lines changed

Diff for: src/main/scala/devices/tilelink/BootROM.scala

+19-10
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,9 @@ case class BootROMParams(
2222
address: BigInt = 0x10000,
2323
size: Int = 0x10000,
2424
hang: BigInt = 0x10040, // The hang parameter is used as the power-on reset vector
25+
driveResetVector: Boolean = true,
26+
appendDTB: Boolean = true,
27+
name: String = "bootrom",
2528
contentFileName: String)
2629

2730
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
@@ -63,7 +66,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
6366
}
6467
}
6568

66-
case class BootROMLocated(loc: HierarchicalLocation) extends Field[Option[BootROMParams]](None)
69+
case class BootROMLocated(loc: HierarchicalLocation) extends Field[Seq[BootROMParams]](Nil)
6770

6871
object BootROM {
6972
/** BootROM.attach not only instantiates a TLROM and attaches it to the tilelink interconnect
@@ -73,27 +76,33 @@ object BootROM {
7376
def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation)
7477
(implicit p: Parameters): TLROM = {
7578
val tlbus = subsystem.locateTLBusWrapper(where)
76-
val bootROMDomainWrapper = tlbus.generateSynchronousDomain("BootROM").suggestName("bootrom_domain")
79+
val bootROMDomainWrapper = tlbus.generateSynchronousDomain(params.name).suggestName(s"${params.name}_domain")
7780

7881
val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()
7982
lazy val contents = {
8083
val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
8184
val rom = ByteBuffer.wrap(romdata)
82-
rom.array() ++ subsystem.dtb.contents
85+
if (params.appendDTB) {
86+
rom.array() ++ subsystem.dtb.contents
87+
} else {
88+
rom.array()
89+
}
8390
}
8491

8592
val bootrom = bootROMDomainWrapper {
8693
LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
8794
}
8895

89-
bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus, Some("BootROM")) := _ }
96+
bootrom.node := tlbus.coupleTo(params.name){ TLFragmenter(tlbus, Some(params.name)) := _ }
9097
// Drive the `subsystem` reset vector to the `hang` address of this Boot ROM.
91-
subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
92-
InModuleBody {
93-
val reset_vector_source = bootROMResetVectorSourceNode.bundle
94-
require(reset_vector_source.getWidth >= params.hang.bitLength,
95-
s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
96-
bootROMResetVectorSourceNode.bundle := params.hang.U
98+
if (params.driveResetVector) {
99+
subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
100+
InModuleBody {
101+
val reset_vector_source = bootROMResetVectorSourceNode.bundle
102+
require(reset_vector_source.getWidth >= params.hang.bitLength,
103+
s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
104+
bootROMResetVectorSourceNode.bundle := params.hang.U
105+
}
97106
}
98107
bootrom
99108
}

Diff for: src/main/scala/subsystem/Configs.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ class BaseSubsystemConfig extends Config ((site, here, up) => {
5454
beatBytes = 8,
5555
blockBytes = site(CacheBlockBytes))
5656
// Additional device Parameters
57-
case BootROMLocated(InSubsystem) => Some(BootROMParams(contentFileName = "./bootrom/bootrom.img"))
57+
case BootROMLocated(InSubsystem) => Seq(BootROMParams(contentFileName = "./bootrom/bootrom.img"))
5858
case HasTilesExternalResetVectorKey => false
5959
case DebugModuleKey => Some(DefaultDebugModuleParams(64))
6060
case CLINTKey => Some(CLINTParams())

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