Merge pull request #3599 from chipsalliance/ifv

Interface to vector units

Author: jerryz123

Diff for: src/main/resources/vsrc/RoccBlackBox.v

@@ -119,6 +119,7 @@ module RoccBlackBox
     input                                rocc_mem_s2_xcpt_ae_ld,
     input                                rocc_mem_s2_xcpt_ae_st,
     input                                rocc_mem_ordered,
+    input                                rocc_mem_store_pending,
     input                                rocc_mem_perf_acquire,
     input                                rocc_mem_perf_release,
     input                                rocc_mem_perf_grant,
@@ -159,6 +160,7 @@ module RoccBlackBox
     output [fLen:0]                      rocc_fpu_req_bits_in1,
     output [fLen:0]                      rocc_fpu_req_bits_in2,
     output [fLen:0]                      rocc_fpu_req_bits_in3,
+    output                               rocc_fpu_req_bits_vec,
     output                               rocc_fpu_resp_ready,
     input                                rocc_fpu_resp_valid,
     input [fLen:0]                       rocc_fpu_resp_bits_data,

Diff for: src/main/scala/rocket/AMOALU.scala

@@ -10,6 +10,7 @@ import org.chipsalliance.cde.config.Parameters
 class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
   val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W))
   size := typ
+  val dat_padded = dat.pad(maxSize*8)
   def misaligned: Bool =
     (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR
 
@@ -24,8 +25,8 @@ class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
   }
 
   protected def genData(i: Int): UInt =
-    if (i >= log2Up(maxSize)) dat
-    else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat((8 << i)-1,0)), genData(i+1))
+    if (i >= log2Up(maxSize)) dat_padded
+    else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1))
 
   def data = genData(0)
   def wordData = genData(2)

Diff for: src/main/scala/rocket/CSR.scala

@@ -245,6 +245,7 @@ class CSRDecodeIO(implicit p: Parameters) extends CoreBundle {
   val fp_illegal = Output(Bool())
   val vector_illegal = Output(Bool())
   val fp_csr = Output(Bool())
+  val vector_csr = Output(Bool())
   val rocc_illegal = Output(Bool())
   val read_illegal = Output(Bool())
   val write_illegal = Output(Bool())
@@ -914,6 +915,7 @@ class CSRFile(
     io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a')
     io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a')
     io_dec.fp_csr := decodeFast(fp_csrs.keys.toList)
+    io_dec.vector_csr := decodeFast(vector_csrs.keys.toList)
     io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a')
     val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) ||
       usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U

Diff for: src/main/scala/rocket/DCache.scala

@@ -93,7 +93,7 @@ class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(i
 
 class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) {
   val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2)))
-  val s1_resp = Output(new TLBResp)
+  val s1_resp = Output(new TLBResp(coreDataBytes.log2))
   val s2_kill = Input(Bool())
 }
 
@@ -926,6 +926,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val s1_isSlavePortAccess = s1_req.no_xcpt
   val s2_isSlavePortAccess = s2_req.no_xcpt
   io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess || s2_valid && !s2_isSlavePortAccess || cached_grant_wait || uncachedInFlight.asUInt.orR)
+  io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) || uncachedInFlight.asUInt.orR
 
   val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack
   io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt))

Diff for: src/main/scala/rocket/DebugROB.scala

@@ -29,7 +29,6 @@ class WidenedTracedInstruction extends Bundle {
 // These is not synthesizable, they use a C++ blackbox to implement the
 // write-back reordering
 class DebugROBPushTrace(implicit val p: Parameters) extends BlackBox with HasBlackBoxResource with HasCoreParameters {
-  require(traceHasWdata && (vLen max xLen) <= 512)
   val io = IO(new Bundle {
     val clock = Input(Clock())
     val reset = Input(Bool())
@@ -45,7 +44,6 @@ class DebugROBPushTrace(implicit val p: Parameters) extends BlackBox with HasBla
 
 class DebugROBPushWb(implicit val p: Parameters) extends BlackBox
     with HasBlackBoxResource with HasCoreParameters {
-  require(traceHasWdata && (vLen max xLen) <= 512)
   val io = IO(new Bundle {
     val clock = Input(Clock())
     val reset = Input(Bool())
@@ -59,7 +57,6 @@ class DebugROBPushWb(implicit val p: Parameters) extends BlackBox
 }
 
 class DebugROBPopTrace(implicit val p: Parameters) extends BlackBox with HasBlackBoxResource with HasCoreParameters {
-  require(traceHasWdata && (vLen max xLen) <= 512)
   val io = IO(new Bundle {
     val clock = Input(Clock())
     val reset = Input(Bool())

Diff for: src/main/scala/rocket/HellaCache.scala

@@ -187,6 +187,7 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
   val s2_gpa_is_pte = Input(Bool())
   val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp)))
   val ordered = Input(Bool())
+  val store_pending = Input(Bool()) // there is a store in a store buffer somewhere
   val perf = Input(new HellaCachePerfEvents())
 
   val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself?

Diff for: src/main/scala/rocket/HellaCacheArbiter.scala

@@ -63,6 +63,7 @@ class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
       io.requestor(i).s2_gpa := io.mem.s2_gpa
       io.requestor(i).s2_gpa_is_pte := io.mem.s2_gpa_is_pte
       io.requestor(i).ordered := io.mem.ordered
+      io.requestor(i).store_pending := io.mem.store_pending
       io.requestor(i).perf := io.mem.perf
       io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === i.U
       io.requestor(i).s2_nack_cause_raw := io.mem.s2_nack_cause_raw

Diff for: src/main/scala/rocket/IDecode.scala

@@ -44,6 +44,7 @@ class IntCtrlSigs(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends Bu
   val fence = Bool()
   val amo = Bool()
   val dp = Bool()
+  val vec = Bool()
 
   def default: List[BitPat] =
                 //           jal                                                                 renf1               fence.i
@@ -433,6 +434,15 @@ class D64Decode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends Deco
     FCVT_D_LU-> List(Y,Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  aluFn.FN_X,     N,M_X,        N,N,N,Y,N,N,N,CSR.N,N,N,N,Y))
 }
 
+class VCFGDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants
+{
+  val table: Array[(BitPat, List[BitPat])] = Array(
+    VSETVLI  -> List(Y,N,N,N,N,N,N,Y,A2_X,   A1_X,   IMM_X, DW_X,  aluFn.FN_X,     N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
+    VSETIVLI -> List(Y,N,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  aluFn.FN_X,     N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
+    VSETVL   -> List(Y,N,N,N,N,N,Y,Y,A2_X,   A1_X,   IMM_X, DW_X,  aluFn.FN_X,     N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
+}
+
+
 class RoCCDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants
 {
   val table: Array[(BitPat, List[BitPat])] = Array(

Diff for: src/main/scala/rocket/NBDcache.scala

@@ -56,6 +56,7 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa
     val mem_access = Decoupled(new TLBundleA(edge.bundle))
     val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle)))
     val replay_next = Output(Bool())
+    val store_pending = Output(Bool())
   })
 
   def beatOffset(addr: UInt) = addr.extract(beatOffBits - 1, wordOffBits)
@@ -119,6 +120,7 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa
   io.resp.bits.data_word_bypass := loadgen.wordData
   io.resp.bits.store_data := req.data
   io.resp.bits.replay := true.B
+  io.store_pending := state =/= s_idle && isWrite(req.cmd)
 
   when (io.req.fire) {
     req := io.req.bits
@@ -335,6 +337,7 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu
     val probe_rdy = Output(Bool())
     val fence_rdy = Output(Bool())
     val replay_next = Output(Bool())
+    val store_pending = Output(Bool())
   })
 
   // determine if the request is cacheable or not
@@ -443,6 +446,8 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu
   TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access))
   TLArbiter.lowestFromSeq(edge, io.mem_finish,  mshrs.map(_.io.mem_finish))
 
+  io.store_pending := sdq_val =/= 0.U || mmios.map(_.io.store_pending).orR
+
   io.resp <> resp_arb.io.out
   io.req.ready := Mux(!cacheable,
                     mmio_rdy,
@@ -1051,6 +1056,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
   io.cpu.resp.bits.data_word_bypass := loadgen.wordData
   io.cpu.resp.bits.data_raw := s2_data_word
   io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
+  io.cpu.store_pending := mshrs.io.store_pending
   io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next
 
   val s1_xcpt_valid = dtlb.io.req.valid && !s1_nack