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Merge pull request #3724 from tymcauley/new-chisel-anno-api
Update to Chisel 6.7, use new annotation API
2 parents 9fcd186 + 5d76b41 commit a54937e

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Diff for: build.sc

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Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ object v {
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val scala = "2.13.12"
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// the first version in this Map is the mainly supported version which will be used to run tests
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val chiselCrossVersions = Map(
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"5.1.0" -> (ivy"org.chipsalliance::chisel:5.1.0", ivy"org.chipsalliance:::chisel-plugin:5.1.0"),
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"6.7.0" -> (ivy"org.chipsalliance::chisel:6.7.0", ivy"org.chipsalliance:::chisel-plugin:6.7.0"),
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// build from project from source
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"source" -> (ivy"org.chipsalliance::chisel:99", ivy"org.chipsalliance:::chisel-plugin:99"),
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)

Diff for: src/main/scala/rocket/DCache.scala

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@@ -25,9 +25,7 @@ import freechips.rocketchip.util.SeqBoolBitwiseOps
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// TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits
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trait InlineInstance { self: chisel3.experimental.BaseModule =>
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chisel3.experimental.annotate(
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new chisel3.experimental.ChiselAnnotation {
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def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } )
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chisel3.experimental.annotate(self)(Seq(firrtl.passes.InlineAnnotation(self.toNamed)))
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}
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class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p)

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