Resolve no-implicit-clock error with AXI4 monitors

If a user enables AXI4 Monitors (using `AXI4MonitorBuilder`), they'll
get a no-implicit-clock error at this point, which isn't easy to track
down. Chipyard worked around a similar problem with TileLink Monitors
here: ucb-bar/chipyard#1868

Author: tymcauley

Diff for: src/main/scala/subsystem/Ports.scala

@@ -105,8 +105,9 @@ trait CanHaveMasterAXI4MemPort { this: BaseSubsystem =>
     })
 
     mbus.coupleTo(s"memory_controller_port_named_$portName") {
-      (memAXI4Node
-        := AXI4UserYanker()
+      // Disable monitors on this connection since the class with this trait (i.e. DigitalTop) doesn't provide an
+      // implicit clock for the monitor.
+      (DisableMonitors { implicit p => memAXI4Node := AXI4UserYanker() }
         := AXI4IdIndexer(idBits)
         := TLToAXI4()
         := TLWidthWidget(mbus.beatBytes)