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Merge pull request #3592 from Zephyr-Computing-Systems/aswehla/amba_diplomacy_update
Make AMBA package importing explicit
2 parents f228714 + 9dbe82b commit b33b8dd

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+253
-109
lines changed

Diff for: ‎build.sc

+4-4
Original file line numberDiff line numberDiff line change
@@ -93,12 +93,12 @@ trait Diplomacy
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override def millSourcePath = os.pwd / "dependencies" / "diplomacy" / "diplomacy"
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// dont use chisel from source
96-
def chiselModule = None
97-
def chiselPluginJar = None
96+
def chiselModule = Option.when(crossValue == "source")(chisel)
97+
def chiselPluginJar = T(Option.when(crossValue == "source")(chisel.pluginModule.jar()))
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// use chisel from ivy
100-
def chiselIvy = Some(v.chiselCrossVersions(crossValue)._1)
101-
def chiselPluginIvy = Some(v.chiselCrossVersions(crossValue)._2)
100+
def chiselIvy = Option.when(crossValue != "source")(v.chiselCrossVersions(crossValue)._1)
101+
def chiselPluginIvy = Option.when(crossValue != "source")(v.chiselCrossVersions(crossValue)._2)
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103103
// use CDE from source until published to sonatype
104104
def cdeModule = cde

Diff for: ‎src/main/scala/amba/ahb/AHBLite.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ package freechips.rocketchip.amba.ahb
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import chisel3._
66
import org.chipsalliance.cde.config.Parameters
7-
import freechips.rocketchip.diplomacy._
7+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
88

99
class AHBLite()(implicit p: Parameters) extends LazyModule {
1010
val node = AHBMasterAdapterNode(

Diff for: ‎src/main/scala/amba/ahb/Nodes.scala

+4-1
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,11 @@ package freechips.rocketchip.amba.ahb
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import chisel3._
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import chisel3.experimental.SourceInfo
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import org.chipsalliance.cde.config.{Parameters, Field}
8-
import freechips.rocketchip.diplomacy._
9+
10+
import org.chipsalliance.diplomacy.ValName
11+
import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp, RenderedEdge, OutwardNode, InwardNode, SourceNode, SinkNode, IdentityNode, AdapterNode, MixedNexusNode, NexusNode}
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1013
case object AHBSlaveMonitorBuilder extends Field[AHBSlaveMonitorArgs => AHBSlaveMonitorBase]
1114

Diff for: ‎src/main/scala/amba/ahb/Parameters.scala

+8-3
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@@ -2,11 +2,16 @@
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package freechips.rocketchip.amba.ahb
44

5-
import chisel3.util._
65
import chisel3.experimental.SourceInfo
6+
import chisel3.util._
7+
78
import org.chipsalliance.cde.config.Parameters
8-
import freechips.rocketchip.diplomacy._
9-
import freechips.rocketchip.util._
9+
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import org.chipsalliance.diplomacy.nodes.BaseNode
11+
12+
import freechips.rocketchip.diplomacy.{AddressSet, Resource, RegionType, TransferSizes, Device, ResourceAddress, ResourcePermissions}
13+
import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase}
14+
1015
import scala.math.{max, min}
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1217
case class AHBSlaveParameters(

Diff for: ‎src/main/scala/amba/ahb/RegisterRouter.scala

+10-4
Original file line numberDiff line numberDiff line change
@@ -3,12 +3,18 @@
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package freechips.rocketchip.amba.ahb
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import chisel3._
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import chisel3.util._
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import chisel3.util.{log2Up, log2Ceil, Decoupled}
7+
78
import org.chipsalliance.cde.config.Parameters
8-
import freechips.rocketchip.diplomacy._
9-
import freechips.rocketchip.regmapper._
9+
10+
import org.chipsalliance.diplomacy.ValName
11+
import org.chipsalliance.diplomacy.nodes.{SinkNode}
12+
13+
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
14+
import freechips.rocketchip.regmapper.{RegMapperParams, RegField, RegMapperInput, RegisterRouter, RegMapper}
1015
import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
11-
import freechips.rocketchip.util._
16+
import freechips.rocketchip.util.MaskGen
17+
1218
import scala.math.min
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1420
case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)

Diff for: ‎src/main/scala/amba/ahb/SRAM.scala

+4-2
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,11 @@ package freechips.rocketchip.amba.ahb
55
import chisel3._
66
import chisel3.util._
77
import org.chipsalliance.cde.config.Parameters
8-
import freechips.rocketchip.diplomacy._
9-
import freechips.rocketchip.util._
8+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
9+
10+
import freechips.rocketchip.diplomacy.{AddressSet, DiplomaticSRAM, HasJustOneSeqMem, RegionType, TransferSizes}
1011
import freechips.rocketchip.tilelink.LFSRNoiseMaker
12+
import freechips.rocketchip.util.{MaskGen, DataToAugmentedData, SeqMemToAugmentedSeqMem, PlusArg}
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1214
class AHBRAM(
1315
address: AddressSet,

Diff for: ‎src/main/scala/amba/ahb/Test.scala

+7-3
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@@ -3,12 +3,16 @@
33
package freechips.rocketchip.amba.ahb
44

55
import chisel3._
6+
67
import org.chipsalliance.cde.config.Parameters
8+
9+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp, SimpleLazyModule}
10+
711
import freechips.rocketchip.devices.tilelink.TLTestRAM
8-
import freechips.rocketchip.diplomacy._
12+
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
913
import freechips.rocketchip.regmapper.{RRTest0, RRTest1}
10-
import freechips.rocketchip.tilelink._
11-
import freechips.rocketchip.unittest._
14+
import freechips.rocketchip.tilelink.{TLFuzzer, TLRAMModel, TLToAHB, TLDelayer, TLBuffer, TLErrorEvaluator, TLFragmenter}
15+
import freechips.rocketchip.unittest.{UnitTestModule, UnitTest}
1216

1317
class AHBRRTest0(address: BigInt)(implicit p: Parameters)
1418
extends RRTest0(address)

Diff for: ‎src/main/scala/amba/ahb/ToTL.scala

+10-4
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@@ -4,11 +4,17 @@ package freechips.rocketchip.amba.ahb
44

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import chisel3._
66
import chisel3.util._
7-
import freechips.rocketchip.amba._
7+
88
import org.chipsalliance.cde.config.Parameters
9-
import freechips.rocketchip.diplomacy._
10-
import freechips.rocketchip.tilelink._
11-
import freechips.rocketchip.util._
9+
10+
import org.chipsalliance.diplomacy.ValName
11+
import org.chipsalliance.diplomacy.nodes.{MixedAdapterNode}
12+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
13+
14+
import freechips.rocketchip.amba.{AMBAProtField, AMBAProt}
15+
import freechips.rocketchip.diplomacy.TransferSizes
16+
import freechips.rocketchip.tilelink.{TLImp, TLMasterPortParameters, TLMessages, TLMasterParameters, TLMasterToSlaveTransferSizes}
17+
import freechips.rocketchip.util.{BundleMap, MaskGen, DataToAugmentedData}
1218

1319
case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHBImpSlave, TLImp)(
1420
dFn = { case mp =>

Diff for: ‎src/main/scala/amba/ahb/Xbar.scala

+7-3
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@@ -3,10 +3,14 @@
33
package freechips.rocketchip.amba.ahb
44

55
import chisel3._
6-
import chisel3.util._
6+
import chisel3.util.Mux1H
7+
78
import org.chipsalliance.cde.config.Parameters
8-
import freechips.rocketchip.diplomacy._
9-
import freechips.rocketchip.util._
9+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
10+
11+
import freechips.rocketchip.diplomacy.AddressDecoder
12+
import freechips.rocketchip.util.BundleField
13+
1014

1115
class AHBFanout()(implicit p: Parameters) extends LazyModule {
1216
val node = new AHBFanoutNode(

Diff for: ‎src/main/scala/amba/ahb/package.scala

+1-1
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@@ -2,7 +2,7 @@
22

33
package freechips.rocketchip.amba
44

5-
import freechips.rocketchip.diplomacy._
5+
import org.chipsalliance.diplomacy.nodes.{InwardNodeHandle, OutwardNodeHandle, SimpleNodeHandle}
66

77
package object ahb
88
{

Diff for: ‎src/main/scala/amba/apb/Nodes.scala

+4-1
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@@ -4,8 +4,11 @@ package freechips.rocketchip.amba.apb
44

55
import chisel3._
66
import chisel3.experimental.SourceInfo
7+
78
import org.chipsalliance.cde.config.{Parameters, Field}
8-
import freechips.rocketchip.diplomacy._
9+
10+
import org.chipsalliance.diplomacy.ValName
11+
import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp,RenderedEdge, InwardNode, OutwardNode, SourceNode, SinkNode, NexusNode, IdentityNode}
912

1013
case object APBMonitorBuilder extends Field[APBMonitorArgs => APBMonitorBase]
1114

Diff for: ‎src/main/scala/amba/apb/Parameters.scala

+9-3
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@@ -2,11 +2,17 @@
22

33
package freechips.rocketchip.amba.apb
44

5-
import chisel3.util._
5+
import chisel3.util.{isPow2, log2Up}
66
import chisel3.experimental.SourceInfo
7+
78
import org.chipsalliance.cde.config.Parameters
8-
import freechips.rocketchip.diplomacy._
9-
import freechips.rocketchip.util._
9+
10+
import org.chipsalliance.diplomacy.nodes.BaseNode
11+
12+
import freechips.rocketchip.diplomacy.{AddressSet, Resource, Device, RegionType, ResourceAddress, ResourcePermissions}
13+
14+
import freechips.rocketchip.util.{BundleField, BundleKeyBase, BundleFieldBase}
15+
1016
import scala.math.max
1117

1218
case class APBSlaveParameters(

Diff for: ‎src/main/scala/amba/apb/RegisterRouter.scala

+8-3
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,15 @@
33
package freechips.rocketchip.amba.apb
44

55
import chisel3._
6-
import chisel3.util._
6+
import chisel3.util.{Decoupled, log2Up, log2Ceil}
7+
78
import org.chipsalliance.cde.config.Parameters
8-
import freechips.rocketchip.diplomacy._
9-
import freechips.rocketchip.regmapper._
9+
10+
import org.chipsalliance.diplomacy.ValName
11+
import org.chipsalliance.diplomacy.nodes.SinkNode
12+
13+
import freechips.rocketchip.diplomacy.AddressSet
14+
import freechips.rocketchip.regmapper.{RegField, RegMapperParams, RegMapperInput, RegMapper, RegisterRouter}
1015
import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
1116

1217
case class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)

Diff for: ‎src/main/scala/amba/apb/SRAM.scala

+7-3
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,15 @@
33
package freechips.rocketchip.amba.apb
44

55
import chisel3._
6-
import chisel3.util._
6+
import chisel3.util.{Cat, log2Ceil, RegEnable}
7+
78
import org.chipsalliance.cde.config.Parameters
8-
import freechips.rocketchip.diplomacy._
9-
import freechips.rocketchip.util._
9+
10+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
11+
12+
import freechips.rocketchip.diplomacy.{AddressSet, DiplomaticSRAM, HasJustOneSeqMem, RegionType}
1013
import freechips.rocketchip.tilelink.LFSRNoiseMaker
14+
import freechips.rocketchip.util.SeqMemToAugmentedSeqMem
1115

1216
class APBRAM(
1317
address: AddressSet,

Diff for: ‎src/main/scala/amba/apb/Test.scala

+6-2
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@@ -3,10 +3,14 @@
33
package freechips.rocketchip.amba.apb
44

55
import chisel3._
6+
67
import org.chipsalliance.cde.config.Parameters
7-
import freechips.rocketchip.diplomacy._
8+
9+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
10+
11+
import freechips.rocketchip.diplomacy.{BufferParams, AddressSet}
812
import freechips.rocketchip.regmapper.{RRTest0, RRTest1}
9-
import freechips.rocketchip.tilelink._
13+
import freechips.rocketchip.tilelink.{TLFuzzer, TLRAMModel, TLToAPB, TLDelayer, TLBuffer, TLFragmenter}
1014
import freechips.rocketchip.unittest._
1115

1216
class APBRRTest0(address: BigInt)(implicit p: Parameters)

Diff for: ‎src/main/scala/amba/apb/ToTL.scala

+9-4
Original file line numberDiff line numberDiff line change
@@ -4,11 +4,16 @@ package freechips.rocketchip.amba.apb
44

55
import chisel3._
66
import chisel3.util._
7-
import freechips.rocketchip.amba._
7+
88
import org.chipsalliance.cde.config.Parameters
9-
import freechips.rocketchip.diplomacy._
10-
import freechips.rocketchip.tilelink._
11-
import freechips.rocketchip.util._
9+
10+
import org.chipsalliance.diplomacy.ValName
11+
import org.chipsalliance.diplomacy.nodes.{MixedAdapterNode}
12+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
13+
14+
import freechips.rocketchip.amba.{AMBAProt, AMBAProtField}
15+
import freechips.rocketchip.diplomacy.TransferSizes
16+
import freechips.rocketchip.tilelink.{TLImp, TLMessages, TLMasterPortParameters, TLMasterParameters}
1217

1318
case class APBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(APBImp, TLImp)(
1419
dFn = { mp =>

Diff for: ‎src/main/scala/amba/apb/Xbar.scala

+7-3
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@@ -3,10 +3,14 @@
33
package freechips.rocketchip.amba.apb
44

55
import chisel3._
6-
import chisel3.util._
6+
import chisel3.util.Mux1H
7+
78
import org.chipsalliance.cde.config.Parameters
8-
import freechips.rocketchip.diplomacy._
9-
import freechips.rocketchip.util._
9+
10+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
11+
12+
import freechips.rocketchip.diplomacy.AddressDecoder
13+
import freechips.rocketchip.util.BundleField
1014

1115
class APBFanout()(implicit p: Parameters) extends LazyModule {
1216
val node = new APBNexusNode(

Diff for: ‎src/main/scala/amba/apb/package.scala

+1-1
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@@ -2,7 +2,7 @@
22

33
package freechips.rocketchip.amba
44

5-
import freechips.rocketchip.diplomacy._
5+
import org.chipsalliance.diplomacy.nodes.{InwardNodeHandle, OutwardNodeHandle, SimpleNodeHandle}
66

77
package object apb
88
{

Diff for: ‎src/main/scala/amba/axi4/AsyncCrossing.scala

+8-3
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@@ -3,11 +3,16 @@
33
package freechips.rocketchip.amba.axi4
44

55
import chisel3._
6+
67
import org.chipsalliance.cde.config.Parameters
7-
import freechips.rocketchip.diplomacy._
8-
import freechips.rocketchip.tilelink._
8+
9+
import org.chipsalliance.diplomacy.nodes.{NodeHandle}
10+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
11+
12+
import freechips.rocketchip.diplomacy.{AddressSet, AsynchronousCrossing}
13+
import freechips.rocketchip.tilelink.{TLRAMModel, TLFuzzer, TLToAXI4}
914
import freechips.rocketchip.subsystem.CrossingWrapper
10-
import freechips.rocketchip.util._
15+
import freechips.rocketchip.util.{ToAsyncBundle, FromAsyncBundle, AsyncQueueParams, Pow2ClockDivider}
1116

1217
/**
1318
* Source(Master) side for AXI4 crossing clock domain

Diff for: ‎src/main/scala/amba/axi4/Buffer.scala

+6-1
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@@ -4,8 +4,13 @@ package freechips.rocketchip.amba.axi4
44

55
import chisel3._
66
import chisel3.util.{Queue, IrrevocableIO}
7+
78
import org.chipsalliance.cde.config.Parameters
8-
import freechips.rocketchip.diplomacy._
9+
10+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
11+
12+
import freechips.rocketchip.diplomacy.BufferParams
13+
914
import scala.math.min
1015

1116
/**

Diff for: ‎src/main/scala/amba/axi4/Credited.scala

+6-2
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@@ -3,10 +3,14 @@
33
package freechips.rocketchip.amba.axi4
44

55
import chisel3._
6+
67
import org.chipsalliance.cde.config.Parameters
7-
import freechips.rocketchip.diplomacy._
8-
import freechips.rocketchip.tilelink._
8+
9+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
10+
11+
import freechips.rocketchip.diplomacy.{AddressSet, CreditedCrossing}
912
import freechips.rocketchip.subsystem.CrossingWrapper
13+
import freechips.rocketchip.tilelink._
1014
import freechips.rocketchip.util._
1115

1216
class AXI4CreditedBuffer(delay: AXI4CreditedDelay)(implicit p: Parameters) extends LazyModule

Diff for: ‎src/main/scala/amba/axi4/CrossingHelper.scala

+3-1
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@@ -3,7 +3,9 @@
33
package freechips.rocketchip.amba.axi4
44

55
import org.chipsalliance.cde.config.Parameters
6-
import freechips.rocketchip.diplomacy._
6+
import org.chipsalliance.diplomacy.lazymodule.{LazyScope}
7+
8+
import freechips.rocketchip.diplomacy.{CrossingType, ClockCrossingType, NoCrossing, AsynchronousCrossing, RationalCrossing, SynchronousCrossing, CreditedCrossing}
79
import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing}
810

911
trait AXI4OutwardCrossingHelper {

Diff for: ‎src/main/scala/amba/axi4/Deinterleaver.scala

+5-1
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@@ -5,8 +5,12 @@ package freechips.rocketchip.amba.axi4
55
import chisel3._
66
import chisel3.util.{Cat, isPow2, log2Ceil, ReadyValidIO,
77
log2Up, OHToUInt, Queue, QueueIO, UIntToOH}
8+
89
import org.chipsalliance.cde.config.Parameters
9-
import freechips.rocketchip.diplomacy._
10+
11+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
12+
13+
import freechips.rocketchip.diplomacy.{BufferParams, TransferSizes}
1014
import freechips.rocketchip.util.leftOR
1115

1216
/** This adapter deinterleaves read responses on the R channel.

Diff for: ‎src/main/scala/amba/axi4/Delayer.scala

+5-2
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@@ -3,9 +3,12 @@
33
package freechips.rocketchip.amba.axi4
44

55
import chisel3._
6-
import chisel3.util._
6+
import chisel3.util.IrrevocableIO
7+
78
import org.chipsalliance.cde.config.Parameters
8-
import freechips.rocketchip.diplomacy._
9+
10+
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
11+
912
import freechips.rocketchip.tilelink.LFSRNoiseMaker
1013

1114
/**

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